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FDS6894AZFAIN/a8avaiDual N-Channel Logic Level PWM Optimized PowerTrench MOSFET


FDS6894AZ ,Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFETGeneral Description MOSFETPowerTrenchOctober 2001FDS6894AZ
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FDS6898AZ ,Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFETGeneral Description MOSFETDual N-Channel Logic Level PWM Optimized PowerTrenchOctober 2001FDS6898AZ
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FDS6894AZ
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
FDS6894AZ October 2001 FDS6894AZ Ò Ò Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET General Description Features These N-Channel Logic Level MOSFETs are produced · 8 A, 20 V. R = 17 m W @ V = 4.5 V DS(ON) GS using Fairchild Semiconductor’s advanced R = 20 m W @ V = 2.5 V DS(ON) GS PowerTrench process that has been especially tailored R = 30 m W @ V = 1.8 V DS(ON) GS to minimize the on-state resistance and yet maintain superior switching performance. · Low gate charge (14 nC typical) These devices are well suited for low voltage and · High performance trench technology for extremely battery powered applications where low in-line power low R DS(ON) loss and fast switching are required. · High power and current handling capability D1 D D1 5 4 D D2 D Q1 D2 D 6 3 7 2 G1 SO-8 G S1 Q2 S G2 S 8 1 S2 SO-8 S Pin 1 o Absolute Maximum Ratings T =25 C unless otherwise noted A Symbol Parameter Ratings Units V Drain-Source Voltage 20 V DSS V Gate-Source Voltage V GSS ± 8 I Drain Current – Continuous (Note 1a) 8 A D – Pulsed 32 P W D Power Dissipation for Dual Operation 2 Power Dissipation for Single Operation (Note 1a) 1.6 (Note 1b) 1.0 (Note 1c) 0.9 T , T Operating and Storage Junction Temperature Range –55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W qJA R Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W qJC Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS6894AZ FDS6894AZ 13’’ 12mm 2500 units Ó2001 FDS6894AZ Rev C (W)
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