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FDS6812AFSCN/a174avaiDual N-Channel Logic Level PWM Optimized PowerTrench MOSFET


FDS6812A ,Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFETapplications where low in-line powerloss and fast switching are required.• High power and current h ..
FDS6812A_NL ,Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFETapplications where low in-line powerloss and fast switching are required.• High power and current h ..
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FDS6812A
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
FDS6812A FDS6812A Ò Ò These N-Channel Logic Level MOSFETs are produced · 6.7 A, 20 V.R = 22 m W @ V = 4.5 V using Fairchild Semiconductor’s advancedR = 35 m W @ V = 2.5 V PowerTrench process that has been especially tailored · Low gate charge (12 nC typical) to minimize the on-state resistance and yet maintain superior switching performance. · High performance trench technology for extremely These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. · High power and current handling capability D54 D DQ1 63 D 72 Q2 GS181 S SS2 SO-8S o T=25C unless otherwise notedA RatingsUnits VDrain-Source VoltageV VGate-Source Voltage ±V IDrain Current– ContinuousAD – Pulsed PWDPower Dissipation for Dual Operation2 Power Dissipation for Single Operation 1 (Note 1c) T, TOperating and Storage Junction Temperature Range–55 to +150 °CJ Thermal Characteristics RThermal Resistance, Junction-to-Ambient °C/W q RThermal Resistance, Junction-to-Case °C/W qJC Device MarkingReel SizeTape widthQuantity FDS6812AFDS6812A12mm2500 units Ó FDS6812A Rev B (W)2001 13’’ Device Package Marking and Ordering Information 40(Note 1) JA 78(Note 1a) STG 0.9 (Note 1b) 1.6(Note 1a) 35 6.7(Note 1a) 12GSS DSS 20 ParameterSymbol Absolute Maximum Ratings Pin 1 G2 SO-8 G1 D2 D2 D1 D1 DS(ON) low R GSDS(ON) GSDS(ON) FeaturesGeneral Description MOSFETDual N-Channel Logic Level PWM Optimized PowerTrench November 2001
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