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FDN357NN/AN/a1500avaiN-Channel Logic Level Enhancement Mode Field Effect Transistor


FDN357N ,N-Channel Logic Level Enhancement Mode Field Effect TransistorGeneral Description
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FDN357N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
March 1998 FDN357N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features TM 1.9 A, 30 V,  R = 0.090 W @ V = 4.5 V SuperSOT -3 N-Channel logic level enhancement mode power DS(ON) GS field effect transistors are produced using Fairchild's R = 0.060 W @ V = 10 V. DS(ON) GS proprietary, high cell density, DMOS technology. This very high Industry standard outline SOT-23 surface mount density process is especially tailored to minimize on-state TM package using proprietary SuperSOT -3 design for resistance. These devices are particularly suited for low voltage superior thermal and electrical capabilities. applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast High density cell design for extremely low R . DS(ON) switching, and low in-line power loss are needed in a very small outline surface mount package. Exceptional on-resistance and maximum DC current capability. TM TM SuperSOT -8 SuperSOT -6 SO-8 SOIC-16 SOT-23 SOT-223 D D S S G TM G SuperSOT -3 o Absolute Maximum Ratings T = 25 C unless other wise noted A Symbol Parameter FDN357N Units V Drain-Source Voltage 30 V DSS V Gate-Source Voltage - Continuous ±20 V GSS I Drain/Output Current - Continuous 1.9 A D - Pulsed 10 P Maximum Power Dissipation (Note 1a) 0.5 W D (Note 1b) 0.46 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W qJA Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W R qJC FDN357N Rev.C © 1998 357
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