FDC6321C ,Dual N & P Channel , Digital FETGeneral Description Digital FETDual N & P C321C F O(T = 25 C unless otherwise noted )ATypeV VVo o ..
FDC6322C ,Dual N & P Channel , Digital FETFeaturesThese dual N & P Channel logic level enhancement mode fieldN-Ch 25 V, 0.22 A, R = 5 Ω @ V ..
FDC6323L ,Integrated Load SwitchGeneral Description FDC6323LMarch (TAI V 8 V 1 µ AI V V µ A )V 3 8 VV 8 VV V V VV V VI V 1 ALV 1 ..
FDC6324 ,Integrated Load SwitchFeaturesV=0.2V @ VV, IA, V=1.5 to 8V Integrated Load Switches are produced usingINLV=0.3V @ V=5V, ..
FDC6324L ,Integrated Load SwitchFeaturesThese Integrated Load Switches are produced using Fairchild's V =0.2V @ V =12V, I =1A, V =1 ..
FDC6325L ,Integrated Load SwitchFeaturesThis is particularly suited for compact pVV @ V=5V, IA. R = 0.13 Ω INL)management in port ..
FMS6502MTC24 , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FDC6321C
Dual N & P Channel , Digital FET
April 1999 DC6 hannel , These dual N & P Channel logic level enhancement mode V, 0.68 A, R = 0.45 W @ V V field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This veryP V, -0.46 A, R = 1.1 W @ V V. high density process is especially tailored to minimize direct on-state resistance. This device has been designed operation in 3 V circuits. V< 1.0V. especially for low voltage applications as a replacement forGS(th) digital transistors in load switching applications. Since bias . resistors are not required this dual digital FET can replace several digital transistors with different bias resistors. Replace multiple dual NPN & PNP digital transistors. TMTM Mark:.321 43 52 TM 61 o TA V V V8V IADO 2 PW D ) TrJ 6 R) qJA R qJC © 1999 FDC6321C.RevB °C/W60 (Note 1)Thermal Resistance, Junction-to-Case °C/W140 (Note 1aThermal Resistance, Junction-to-Ambient THERMAL CHARACTERISTICS Human Body Model (100pf / 1500 Ohm) kVElectrostatic Discharge Rating MIL-STD-883D ESD STG °C-55 to 150ature RangeOperating and Storage Temp,T 0.7 (Note 1b 0.9 ) Note 1a ( Power DissipationMaximum -1.5- Pulsed -0.460.68- ContinuousDrain/Output Current , I INGSS -8, Gate-Source Voltage, V CCDSS -2525Drain-Source Voltage, Power Supply Voltage, V UnitsP-ChannelN-ChannelParameterSymbol C unless other wise noted = 25 Absolute Maximum Ratings G1 SuperSOT -6 S2 G2 D1 S1 D2 SOT-223-8SuperSOT-6SuperSOT SOIC-16SO-8 SOT-23 kV Human Body Model>6 ESD ruggednessGate-Source Zener for Very low level gate drive requirements allowing GSDS(ON) -4.5= -Ch -25 GSDS(ON) 4.5= N-Ch 25 Features General Description Digital FETDual N & P C 321C F
