FDB4030L ,N-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)CSymbol Parameter Conditions Min Typ Ma ..
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FDB4030L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
March 1998 FDP4030L / FDB4030L N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel enhancement mode power field effect 20 A, 30 V. R = 0.035 W @ V =10 V DS(ON) GS transistors are produced using Fairchild's proprietary, R = 0.055 W @ V =4.5V. DS(ON) GS high cell density, DMOS technology. This very high Critical DC electrical parameters specified at elevated density process has been especially tailored to minimize temperature. on-state resistance and provide superior switching performance. These devices are particularly suited for Rugged internal source-drain diode can eliminate the low voltage applications such as DC/DC converters and need for an external Zener diode transient suppressor. other battery powered circuits where fast switching, low High density cell design for extremely low R . DS(ON) in-line power loss, and resistance to transients are needed. 175°C maximum junction temperature rating. _______________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FDP4030L FDB4030L Units V Drain-Source Voltage 30 V DSS V Gate-Source Voltage ±20 V GSS I Drain Current - Continuous (Note 1) 20 A D - Pulsed (Note 1) 60 P Total Power Dissipation @ T = 25°C 37.5 W D C Derate above 25°C 0.25 W/°C T ,T Operating and Storage Temperature Range -65 to 175 °C J STG T Maximum lead temperature for soldering purposes, 275 °C L 1/8" from case for 5 seconds THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Case 4 °C/W JC q R Thermal Resistance, Junction-to-Ambient 62.5 °C/W qJA © 1998 FDP4030L Rev.B1
