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EMIF10-1K010F1 |EMIF101K010F1STN/a50000avaiEMI FILTER INCLUDING ESD PROTECTION


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EMIF10-1K010F1
EMI FILTER INCLUDING ESD PROTECTION
EMIF10-1K010F1
July 2002 - Ed: 3C 1/13
PIN CONFIGURATION (Ball Side)

EMI FILTER
INCLUDING ESD PROTECTIONA.S.D.TM
The EMIF10-1K010F1 isa highly integrateddevice designedto suppress EMI/ RFI noiseinallsystems subjected to electromagnetic
interferences. The EMIF10 flip-chip packagingmeans the package sizeis equalto the die size.That's why EMIF10-1K010F1isa very smalldevice.
Additionally, this filter includes an ESD protectioncircuitry which prevents the protected device from
destruction when subjectedto ESD surgesupto15 kV.
DESCRIPTION
: ASDisa trademarkof STMicroelectronics.
Where EMI filteringin ESD sensitive equipmentis
required: Computers and printers Communication systems Mobile phones MCU Boards
MAIN APPLICATIONS
EMI symetrical (I/O) low-pass filter High efficiencyin EMI filtering Very low PCB space consuming: 2.6x 2.6 mm2 Very thin package: 0.65 mm High efficiencyin ESD suppressionon both input output PINS (IEC61000-4-2 level4). High reliability offeredby monolithic integration High reducingof parasitic elements throughin-
tegration& wafer level packaging.
BENEFITS
BASIC CELL CONFIGURATION
EMIF10-1K010F1
IEC61000-4-2 level4 15 KV (air discharge) kV (contact discharge) input& output pins
MIL STD 883C- Method 3015-6 Class3
COMPLIES WITH FOLLOWING STANDARD:
Filtering Behavior
ESD responseto IEC61000-4-2 (16kV Air Dis-
charge)
Capacitance versus reverse applied voltage.
EMIF10-1K010F1
ELECTRICAL CHARACTERISTICS
(Tamb = 25°C)
ABSOLUTE MAXIMUM RATINGS
(Tamb =25°C)
Note1:
To calculate theESD residual voltage, please refertothe paragraph "ESD PROTECTION"on page5.
EMIF10-1K010F1
TECHNICAL INFORMATION

The EMIF10-1K010F1is firstly designed as anEMI/ RFI filter.This low-pass filteris characterizedby the following parameters: Cut-off frequency Insertion loss High frequency
FREQUENCY BEHAVIOR
Fig. A1:
Frequency response curve
FigureA1 gives these parameters,in particular thesignal rejectionat the GSM frequency: 25dB@ 900Mhz 14dB@ 1800Mhz
Fig. A2:
Measurements conditions
EMIF10-1K010F1 addition with the filtering the EMIF10-1K010F1is particularly optimizedto perform ESD protection.ESD protectionis basedon the useof device which clampsat: RIcl br d pp=+ ⋅
This protection functionis splittedin2 stages. As shownin Figure A3, the ESD strikes are clampedbythe first stage S1 and thenits remaining overvoltageis appliedto the second stage through the resis-torR. Sucha configuration makes the output voltage very lowat the Vout level.
ESD PROTECTION
Fig. A3:
ESD clamping behavior havea good approximationof the remaining voltagesat both Vin and Vout stages, we give the typicaldynamic resistance value Rd. By taking into account these following hypothesis: R>>Rd, Rg>>Rd andRload>>Rd,it gives these formulas:
Vinpout RV RV
gbr d g= ⋅+ ⋅
Voutput RV R V d in= ⋅+ ⋅
The resultsof the calculation done for an IEC 1000-4-2 Level4 Contact Discharge surge (Vg=8kV,Rg=330Ω) and Vbr=7V (typ.) give:
Vinput= 31.24V
Voutput= 7.03V
This confirms the very low remaining voltage across the devicetobe protected.Itis also importantto notethatin this approximation the parasitic inductance effect was not taken into account. This couldbe few
tenthsof volts during fewnsat the Vin side. This parasitic effectis not presentat the Vout side due the lowcurrent involved after the series resistanceR.
EMIF10-1K010F1
The early ageing and destructionof IC’sis often dueto latch-up phenomena which mainly inducedby
dV/dt. Thankstoits RC structure, the EMIF10-1K010F1 providesa high immunityto latch-upby integrationof fast edges. (Please referto the responseof the EMIF10-1K010F1 toa3ns edgeon Fig. A9)
The measurements done here after show very clearly (Fig. A5a& A5b) the high efficiencyof the ESDprotection: almostno influenceof the parasitic inductanceson Vout stage Vout clamping voltage very closeto Vbrfor positive surge and closeto groundfor negative one
LATCH-UP PHENOMENA
Fig. A4:
Measurement conditions
Fig.A5:
Remaining voltage at both stages S1 (Vin1) and S2 (Vout1) during ESD surge
Please note that the EMIF10-1K010F1is not only acting for positive ESD surges but also for negative
ones. For negatives surges,it clamps closeto ground voltageas shownin Fig. A5b.
EMIF10-1K010F1
Fig. A6:
Rd measurement current wave
Note:
Dynamic resistance measurement the valueof the dynamic resistance remains
stable fora surge duration lower than 20μs, the2.5μs rectangular surgeis well adapted. Inaddition both rise and fall times are optimizedto
avoid any parasitic phenomenon during themeasurementof Rd
CROSSTALK BEHAVIOR
Fig. A7:
Crosstalk phenomena- Crosstalk phenomena
The crosstalk phenomena are dueto the coupling between2 lines. The coupling factor(12or 21)
increases when the gap across lines decreases, particularlyin silicon dice.In the example above the expected signalon load RL2is VG2,in fact the actual voltageat this point hasgotan extra value 21VG1. This partof the VG1 signal represents the effectof the crosstalk phenomenonofthe line1on the line2.
This phenomenon hastobe taken into account when the drivers impose fast digital dataor high frequencyanalog signalsin the disturbing line. The perturbed line willbe more affectedifit works with low voltagesignalor high load impedance (few kW). The following chapters give the valueof both digital and analog
crosstalk.
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