DS92LV040ATLQA ,4 Channel Bus LVDS TransceiverElectrical CharacteristicsOver recommended operating supply voltage and temperature ranges unless o ..
DS92LV040ATLQA ,4 Channel Bus LVDS TransceiverApplications Information Section formore details.) n Product offered in 44 pin LLP (Leadless Leadfr ..
DS92LV0421SQ/NOPB ,10Features 3 DescriptionThe DS92LV042x chipset translates a Channel Link1• 5-Channel (4 Data + 1 Cloc ..
DS92LV090A ,9 Channel Bus LVDS TransceiverFeaturesn Bus LVDS SignalingThe DS92LV090A is one in a series of Bus LVDS transceiv-ers designed sp ..
DS92LV090ATVEH ,9 Channel Bus LVDS TransceiverFeaturesn Bus LVDS SignalingThe DS92LV090A is one in a series of Bus LVDS transceiv-ers designed sp ..
DS92LV090ATVEH/NOPB ,9 Channel Bus LVDS Transceiver 64-LQFP -40 to 85features a flow through pinID200mV out which allows easy PCB routing for short stubsbetween its pin ..
DS92LV040ATLQA
4 Channel Bus LVDS Transceiver
DS92LV040A Channel Bus LVDS Transceiver
General DescriptionThe DS92LV040Ais oneina seriesof Bus LVDS transceiv-
ers designed specificallyfor high speed, low power back-
planeor cable interfaces. The device operates froma single
3.3V power supply and includes four differential line drivers
and four receivers.To minimize bus loading,the driver out-
puts and receiver inputsare internally connected. Thedevice
also featuresa flow throughpinout which allows easy PCB
routingfor short stubs betweenits pins andthe connector.
The driver translates3V LVTTL levels (single-ended)to dif-
ferential Bus LVDS (BLVDS) output levels. This allowsfor
high speed operation while consuming minimal power and
reducing EMI.In addition, the differential signaling provides
common mode noise rejection greater than ±1V.
The receiver thresholdis less than +0/−70 mV. The receiver
translates the differential Bus LVDSto standard (LVTTL/
LVCMOS) levels. (See Applications Information Sectionfor
more details.)
Features Bus LVDS Signaling Propagation delay: Driver 2.3ns max, Receiver 3.2ns
max Low power CMOS design 100% Transition time 1ns driver typical, 1.3ns receiver
typical High Signaling Rate Capability (above 155 Mbps) 0.1Vto 2.3V Common Mode Rangefor VID= 200mV70 mV Receiver Sensitivity Supports open and terminated failsafeon port pins 3.3V operation Glitch free power up/down (Driver& Receiver disabled) Light Bus Loading(5pF typical) per Bus LVDS load Designedfor Double Termination Applications Balanced Output Impedance Product offeredin44pin LLP (Leadless Leadframe
Package) package High impedance Bus pinson poweroff (VCC= 0V)
Simplified Functional DiagramAugust 2002
DS92L
V040A
Channel
Bus
VDS
ransceiver
