DS90CR482VS ,48-Bit LVDS Channel Link DeserializerFeaturesreduction. Long distance parallel single-ended buses typi-n 3.168 Gbits/sec bandwidth with ..
DS90CR482VS/NOPB ,48-Bit LVDS Channel Link Deserializer
DS90CR484AVJD/NOPB ,48-Bit LVDS Channel Link SER/DESFEATUREScable reduction. Long distance parallel single-ended2• Up to 5.38 Gbits/sec Bandwidthbuses ..
DS90CR485VS ,133MHz LVDS 48-bit Channel Link Serializer
DS90CR485VS ,133MHz LVDS 48-bit Channel Link Serializer
DS90CR485VS/NOPB ,133MHz LVDS 48-bit Channel Link Serializer 100-TQFP -10 to 70Electrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CR481VJD-DS90CR482VS
48-Bit LVDS Channel Link Serializer
DS90CR481/ DS90CR482
48-Bit LVDS Channel Link SER/DES − 65- 112 MHz
General DescriptionThe DS90CR481 transmitter converts48 bitsof CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling)
data streams. Aphase-locked transmit clockis transmittedin
parallel with the data streams overa ninth LVDS link. Every
cycleofthe transmit clock48 bitsof input dataare sampled
and transmitted. The DS90CR482 receiver converts the
LVDS data streams back into48 bitsof LVCMOS/TTL data.a transmit clock frequencyof 112MHz,48 bitsof TTL data
are transmittedata rateof 672Mbpsper LVDS data channel.
Usinga 112MHz clock, the data throughputis 5.38Gbit/s
(672Mbytes/s).Ata transmit clock frequencyof 112MHz,48
bitsof TTL data are transmittedata rateof 672Mbps per
LVDS data channel. Usinga 66MHz clock,the data through-
putis 3.168Gbit/s (396Mbytes/s).
The multiplexingof data lines providesa substantial cable
reduction. Long distance parallel single-ended buses typi-
cally requirea ground wire per active signal (and have very
limited noise rejection capability). Thus,fora 48-bit wide
data and one clock,upto98 conductors are required. With
this Channel Link chipsetas fewas19 conductors(8 data
pairs,1 clock pair anda minimumof one ground) are
needed. This providesan 80% reductionin cable width,
which providesa system cost savings, reduces connector
physical size and cost, and reduces shielding requirements
duetothe cables’ smaller form factor.
The48 CMOS/TTL inputs can supporta varietyof signal
combinations. For example,6 8-bit wordsor5 9-bit (byte+
parity) and3 controls.
The DS90CR481/DS90CR482 chipsetis improved over prior
generationsof Channel Link devices and offers higher band-
width support and longer cable drive with three areasof
enhancement.To increase bandwidth, the maximum clock
rateis increasedto 112 MHz and8 serialized LVDS outputs
are provided. Cable driveis enhanced witha user selectable
pre-emphasis feature that provides additional output current
during transitionsto counteract cable loading effects. Op-
tional DC balancingona cycle-to-cycle basis,is also pro-
videdto reduceISI (Inter-Symbol Interference). With pre-
emphasis and DC balancing,a low distortion eye-patternis
providedat the receiver endof the cable.A cable deskew
capability has been addedto deskew long cablesof pair-to-
pair skewofupto +/−1 LVDS databit time (upto80 MHz
Clock Rate). These three enhancements allow cables5+
metersin lengthtobe driven.
The chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features 3.168 Gbits/sec bandwidth with66 MHz Clock 5.376 Gbits/sec bandwidth with 112 MHz Clock65- 112 MHz input clock support LVDS SER/DES reduces cable and connector size Pre-emphasis reduces cable loading effects Optional DC balance encoding reducesISI distortion Cable Deskewof +/−1 LVDS databit time (upto80
MHz Clock Rate)5V Tolerant TxIN and control input pins Flow through pinoutfor easy PCB design +3.3V supply voltage Transmitter rejects cycle-to-cycle jitter Conformsto ANSI/TIA/EIA-644-1995 LVDS Standard
Generalized Block Diagrams (DS90CR481 and DS90CR482)May 2002
DS90CR481/DS90CR482
48-Bit
VDS
Channel
Link
SER/DES
MHz
