DS90CR288AMTD/NOPB ,+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link ReceiverElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
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DS90CR288AMTD/NOPB
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver
DS90CR287, DS90CR288A
www.ti.com SNLS056G –OCTOBER 1999–REVISED MARCH 2013
DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS
28-Bit Channel Link- 85MHz
Checkfor Samples: DS90CR287, DS90CR288A
1FEATURES DESCRIPTIONThe DS90CR287 transmitter converts 28 bits of
• 20to85 MHz Shift Clock Support LVCMOS/LVTTL data into four LVDS (Low Voltage
• 50% Duty Cycle on Receiver Output Clock Differential Signaling) data streams.A phase-locked
2.5/0ns Set& Hold Times on TxINPUTs transmit clockis transmittedin parallel with the data
streams overa fifth LVDS link. Every cycleof the
• Low Power Consumption transmit clock 28 bitsof input data are sampled and
• ±1V Common-Mode Range (around +1.2V) transmitted.
• Narrow Bus Reduces Cable Size and Cost The DS90CR288A receiver converts the four LVDS
• Upto 2.38 Gbps Throughput data streams back into 28 bitsof LVCMOS/LVTTL
Upto 297.5 Mbytes/sec Bandwidth data.Ata transmit clock frequencyof85 MHz,28 bits TTL data are transmittedata rateof 595 Mbps per
• 345 mV (typ) Swing LVDS Devices for Low EMI LVDS data channel. Usinga 85 MHz clock, the data
• PLL Requires no External Components throughputis 2.38 Gbit/s (297.5 Mbytes/sec).
• Rising Edge Data Strobe This chipsetis an ideal meansto solve EMI and
• Compatible with TIA/EIA-644 LVDS Standard cable size problems associated with wide, high-speed
Low Profile 56-Lead TSSOP Package TTL interfaces.
Block Diagram Figure
See Package (TSSOP) See Package Number DGG-56
