DS90CR218MTDX ,+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link ReceiverBlock DiagramsDS90CR217 DS90CR21810087101 10087127Order Number DS90CR217MTD Order Number DS90CR218M ..
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DS90CR218MTD-DS90CR218MTDX
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver
DS90CR218
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link Receiver- 75 MHz
General DescriptionThe DS90CR217 (see DS90CR217/218A datasheet) trans-
mitter converts21 bitsof CMOS/TTL data into three LVDS
(Low Voltage Differential Signaling) data streams.A phase-
locked transmit clockis transmittedin parallel with the data
streams overa fourth LVDS link. Every cycleofthe transmit
clock21 bitsof input dataare sampled and transmitted. The
DS90CR218 receiver convertsthe three LVDS data streams
back into21 bitsof CMOS/TTL data.Ata transmit clock
frequencyof75 MHz,21 bitsof TTL data are transmittedat rateof 525 Mbpsper LVDS data channel. Usinga75 MHz
clock,the data throughputis 1.575 Gbit/s (197 Mbytes/sec).
Complete specificationsfor the DS90CR217 are locatedin
the DS90CR217/DS90CR218A datasheet. The DS90CR217
supports clock rates from20to85 MHz.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features20to75 MHz shift clock support 50% duty cycleon receiver output clock Best-in-Class Set& Hold Timeson TxINPUTs and
RxOUTPUTs Low power consumptionTx+Rx Powerdown mode <400μW (max) ±1V common-mode range (around +1.2V) Narrow bus reduces cable size and cost Upto 1.575 Gbps throughput Upto 197 Mbytes/sec bandwidth 345 mV (typ) swing LVDS devicesfor low EMI PLL requiresno external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 48-lead TSSOP package
Block Diagrams
DS90CR217 DS90CR218Order Number DS90CR217MTD
SeeNS Package Number MTD48
(See DS90CR217/DS90CR218A Datasheet)
Order Number DS90CR218MTD
SeeNS Package Number MTD48
May 2002
DS90CR218
+3.3V
Rising
Edge
Data
Strobe
VDS
21-Bit
Channel
Link
Receiver
MHz
