DS90CR214MTD ,21-Bit Channel LinkDS90CR213/DS90CR214 21-Bit Channel Link—66 MHzJuly 1997DS90CR213/DS90CR21421-Bit Channel Link—66 MH ..
DS90CR214MTD ,21-Bit Channel LinkBlock DiagramsDS90CR213DS90CR214DS012888-27DS012888-1Order Number DS90CR213MTDOrder Number DS90CR21 ..
DS90CR214MTD ,21-Bit Channel LinkFeaturesLVDS data streams back into 21 bits of CMOS/TTL data. Ata transmit clock frequency of 66 MH ..
DS90CR214MTD ,21-Bit Channel LinkBlock DiagramsDS90CR213DS90CR214DS012888-27DS012888-1Order Number DS90CR213MTDOrder Number DS90CR21 ..
DS90CR214MTDX ,21-Bit Channel LinkFeaturesLVDS data streams back into 21 bits of CMOS/TTL data. Ata transmit clock frequency of 66 MH ..
DS90CR215 ,+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel LinkFeaturesparallel with the data streams over a fourth LVDS link. Everyn Single +3.3V supplycycle of ..
DS90CR213MTD-DS90CR214MTD-DS90CR214MTDX
21-Bit Channel Link
DS90CR213/DS90CR214
21-Bit Channel Link—66 MHz
General DescriptionThe DS90CR213 transmitter converts21 bitsof CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. Aphase-locked transmit clockis transmittedin
parallel withthe data streams overa fourth LVDS link. Every
cycleofthe transmit clock21 bitsof input dataare sampled
and transmitted. The DS90CR214 receiver converts the
LVDS data streams back into21 bitsof CMOS/TTL data.At transmit clock frequencyof66 MHz,21 bitsof TTL dataare
transmittedata rateof 462 Mbps per LVDS data channel.
Usinga66 MHz clock,the data throughputis 1.386 Gbit/s
(173 Mbytes/s).
The multiplexingof the data lines providesa substantial
cable reduction. Long distance parallel single-ended buses
typically requirea ground wire per active signal (and have
very limited noise rejection capability). Thus,fora 21-bitwide
data and one clock,upto44 conductors are required. With
the Channel Link chipsetas fewas9 conductors(3 data
pairs,1 clock pair anda minimumof one ground) are
needed. This providesan 80% reductionin required cable
width, which providesa system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments dueto the cable’s smaller form factor.
The21 CMOS/TTL inputs can supporta varietyof signal
combinations. For example,5 4-bit nibbles (byte+ parity)or 9-bit (byte+3 parity) and1 control.
Features66 MHz Clock Support Upto 173 Mbytes/s bandwidth Low power CMOS design (<610 mW) Power-down mode (<0.5 mW total) Upto 1.386 Gbit/s data throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devicesfor low EMI PLL requiresno external components Low profile 48-lead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
DS90CR213DS012888-27
Order Number DS90CR213MTD
SeeNS Package Number MTD48
DS90CR214DS012888-1
Order Number DS90CR214MTD
SeeNS Package Number MTD48July 1997
DS90CR213/DS90CR214
21-Bit
Channel
Link
MHz
