DS90CF383BMTX/NOPB ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 56-TSSOP -10 to 70FEATURES DESCRIPTIONThe DS90CF383B transmitter converts 28 bits of23• No Special Start-up Sequence ..
DS90CF383MTD ,+ 3.3V LVDS 24-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF384AMTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF384A receiver ..
DS90CF384AMTD. ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF384AMTD/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkFEATURES DESCRIPTIONThe DS90CF384A receiver converts the four LVDS2• 20 to 65 MHz Shift Clock Suppo ..
DS90CF384AMTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzElectrical Characteristics (Continued)Note 1: “Absolute Maximum Ratings” are those values beyond wh ..
DS90CF383BMTX/NOPB
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 56-TSSOP -10 to 70
DS90CF383B
www.ti.com SNLS178E –JULY 2004–REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
Checkfor Samples: DS90CF383B
1FEATURES DESCRIPTIONThe DS90CF383B transmitter converts 28 bits of
23• No Special Start-up Sequence Required CMOS/TTL data into four LVDS (Low Voltage
Between Clock/Data and /PD Pins. Input Signal Differential Signaling) data streams.A phase-locked
(Clock and Data) Canbe Applied Either Before transmit clockis transmittedin parallel with the data
or After the Deviceis Powered. streams overa fifth LVDS link. Every cycleof the
Support Spread Spectrum Clocking Upto transmit clock 28 bitsof input data are sampled and
100KHz Frequency Modulation& Deviationsof transmitted.Ata transmit clock frequencyof65 MHz, bitsof RGB data and3 bitsof LCD timing and
±2.5% Center Spreador −5% Down Spread.control data (FPLINE, FPFRAME, DRDY) are
• "Input Clock Detection" Feature Will Pull All transmittedata rateof 455 Mbps per LVDS data
LVDS Pairsto Logic Low when Input Clockis channel. Usinga 65 MHz clock, the data throughput
Missing and When /PD Pinis Logic High. is 227 Mbytes/sec. The DS90CF383Bis fixed asa
• 18to68 MHz Shift Clock Support Falling edge strobe transmitter and will interoperate
witha Falling edge strobe Receiver (DS90CF386)
• Best–in–Class Set& Hold Times on TxINPUTs without any translation logic.
• Tx Power Consumption< 130 mW (typ)
@65MHz Grayscale This chipsetis an ideal meansto solve EMI and
cable size problems associated with wide, high speed
• 40% Less Power Dissipation Than BiCMOS TTL interfaces.
Alternatives Tx Power-down Mode< 60μW (typ) Supports VGA, SVGA, XGA and Dual Pixel
SXGA. Narrow Cus Reduces Cable Size and Cost Upto 1.8 Gbps Throughput Upto 227 Megabytes/sec Bandwidth 345 mV (typ) Swing LVDS Devices for Low EMI PLL Requires No External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 56-Lead TSSOP Package for:
