DS80CH11 Fast Delivery |IC PHOENIX CO.,LIMITED

DS80CH11 ,System Energy ManagerGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS80CH11-E02 ,System Energy ManagerGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS80CH11-E02 ,System Energy ManagerDS80CH11DS80CH11System Energy ManagerPRODUCT SPECIFICATIONV2.1011200 1/88Downloaded from: http://ww ..
DS80PCI800SQE/NOPB ,2.5 Gbps/5.0 Gbps/8.0 Gbps 8 Channel PCI Express Repeater w/ Equalization & De-Emphasis 54-WQFN -40 to 85Features 2 Applications1• Comprehensive Family, Proven System • PCI Express Gen-1, Gen-2, and Gen-3 ..
DS8113-JNG+T&R ,Smart Card Interfaceapplications.1.8V ±10%, 30mA (max)An EMV Level 1 library (written for the MAXQ2000♦ Automatic Card ..
DS83C520C03 ,EPROM/ROM High-Speed Microcontrollersfeatures of the DS87C520 will apply to the DS83C520, with the exception of EPROM-specific
ECH8401 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsOrdering number : ENN8148 ECH8402N-Channel Silicon MOSFETGeneral-Purpose Switching DeviceECH8402App ..
ECH8410 ,N-Channel Power MOSFET, 30V, 12A, 10mOhm, Single ECH8Maximum RatingsParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 30 VDSSGate-to-Sou ..
ECH8601 ,Nch+NchAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8604 ,N CHANNEL MOS SILICON TRANSISTOR

DS80CH11
System Energy Manager
DS80CH11
System Energy Manager
DS80CH11
011200 1/88
PRODUCT SPECIFICATION
V2.1
DS80CH11
011200 2/88
1.0GENERAL DESCRIPTION5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1OVERVIEW5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2DETAILED FEATURE SUMMARY7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3CONVENTIONS7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4ADDITIONAL REFERENCES7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.0PIN DESCRIPTION8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1PIN FUNCTION SUMMARY9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2PIN CHARACTERISTICS14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.0CORE MICROCONTROLLER19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1CORE MICRO OVERVIEW19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2INSTRUCTION SET SUMMARY19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3SPEED IMPROVEMENT21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4INSTRUCTION SET ADDITIONAL REFERENCES21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5RESET21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6INTERRUPT CONTROL22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.0MEMORY RESOURCES24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1OVERVIEW24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2DATA MEMORY ACCESS24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1Stretch Memory Cycle24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2Dual Data Pointer25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3EXTERNAL MEMORY INTERFACE25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4DIRECT (SCRATCHPAD) RAM ACCESS25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5SPECIAL FUNCTION REGISTERS25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0CORE I/O RESOURCES30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1PROGRAMMABLE TIMERS30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2SERIAL PORTS30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3WATCHDOG TIMER30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4PARALLEL I/O PORTS31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1Alternate Pin Function Summary31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.02–Wire SERIAL INTERFACE33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1INTRODUCTION33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2REGISTER DESCRIPTION34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.12WFSx – 2–Wire Frequency Select Registers34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.22WDATx – 2–Wire Data I/O Registers34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.32WSADRx – 2–Wire Slave Address Registers34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.42WCONx – 2–Wire Control Registers35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.52WSTAT1x – 2–Wire Status Register 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.62WSTAT2x – 2–Wire Status Register 236. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3OPERATION DESCRIPTION37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1Master Transmit38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2Master Receive39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3Slave Receive40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLE OF CONTENTS
DS80CH11
011200 3/88
6.3.4Slave Transmit41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5Bus Monitor Mode Operation43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.0A/D CONVERTER44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1OVERVIEW44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2ANALOG POWER / SLEEP MODE44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3REFERENCE OPTION45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4SAR A/D CONVERTER45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5CONVERSION TIME46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6WINDOW COMPARATOR47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7A/D OPERATION48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8A/D SPECIAL FUNCTION REGISTERS49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.1ADCON1 – A/D Control Register 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.2ADCON2 – A/D Control Register 250. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.3ADMSB – A/D Result Most Significant Byte50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.4ADLSB – A/D Result Least Significant Byte51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.5WINHI – A/D Window Comparator High Byte51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.6WINLO – A/D Window Comparator Low Byte51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.0ACTIVITY MONITOR/LED CONTROL52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1OVERVIEW52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2ACTIVITY MONITOR INPUT OPERATION52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3AME – ACTIVITY MONITOR ENABLE REGISTER53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4AMQ – ACTIVITY MONITOR QUALIFIER REGISTER53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5AMP – ACTIVITY MONITOR POLARITY REGISTER54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6AMF – ACTIVITY MONITOR FLAG REGISTER54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7LED CONTROL54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.0HOST INTERFACE PORTS55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1OVERVIEW55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2REGISTER MAPPING55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3KBDIN / PMDIN – DATA REGISTERS56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4KBSTAT / PMSTAT – STATUS REGISTERS57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5KBDOUT / PMDOUT – OUTPUT DATA REGISTERS58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.0KEYBOARD SCANNING PORTS59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1OVERVIEW59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2KEY SCAN OUTPUTS59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3KEY SCAN INPUTS59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4KDE – KEY DETECT ENABLE REGISTER59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5KDF – KEYBOARD DETECT FLAG REGISTER59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.0PULSE WIDTH MODULATORS60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1FUNCTION OVERVIEW60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2PRESCALER60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3PWM CLOCK GENERATORS60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4PWM PULSE GENERATORS61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5PWM SPECIAL FUNCTION REGISTERS62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.1PW01CS / PW23CS – PWM 0, 1 / PWM 2, 3 Clock Select Registers62. . . . . . . . . . . . . .
11.5.2PW01CON / PW23CON – PWM 0, 1 / PWM 2, 3 Control Register63. . . . . . . . . . . . . . . .
11.5.3PWnFG – PWM n Frequency Generator Registers63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.4PWMn – PWM n Value Registers64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.0MICROCONTROLLER POWER MANAGEMENT66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1POWER–DOWN / POWER–UP OPERATION66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS80CH11
011200 4/88
12.1.1Microcontroller Power Fail Reset66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2LOW POWER OPERATING MODES66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1Slow Clock Mode66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1.1Crystaless Slow Clock Mode67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1.2Slow Clock Mode Operation67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1.3Clock Divider67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1.4Switchback68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1.5Status68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1.6Crystal / Ring Operation68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2Idle Mode71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3Stop Mode and Enhancements71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.0+5.0V ELECTRICAL SPECIFICATIONS74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1ABSOLUTE MAXIMUM RATINGS*74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS74. . . . . . . . . . . . . . . . . . . . . . . . . .
13.3MICROCONTROLLER AC ELECTRICAL CHARACTERISTICS76. . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.1External Program Memory Characteristics76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.2MOVX Using Stretch Memory Cycles77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.3External Clock Characteristics78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.4Serial Port Mode 0 Timing Characteristics78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.5Power Cycle Timing Characteristics79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4SYSTEM INTERFACE DC ELECTRICAL CHARACTERISTICS83. . . . . . . . . . . . . . . . . . . . . . . . . .
13.5HOST I/F AC TIMING CHARACTERISTICS84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.62–Wire AC TIMING CHARACTERISTICS86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7A/D CONVERTER SPECIFICATIONS87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7.1Absolute Maximum Ratings87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7.2A/D Electrical Characteristics87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS80CH11
011200 5/88
1.0GENERAL DESCRIPTION
1.1OVERVIEW
The System Energy Manager is a highly integrated
microcontroller that provides several key features for
systems including key scanning and control, battery
and power management, as well as two 2–Wire serial
I/O Ports. It incorporates the Dallas 8051–compatible
high–speed microcontroller core which has been rede-
signed to eliminate wasted clock and memory cycles.
Every standard 8051 instruction is executed between
1.5 and 3 times faster than the original for the same
crystal speed. Looking at it another way, the high–
speed core achieves the same throughput as a stan-
dard 8051 while using much less power as a result of
fewer required clock cycles. As a result, the firmware
can easily support many tasks required by mobile sys-
tems within a single component.
The controller is designed to off–load battery and power
management tasks from the host CPU and thereby
make possible an efficient solution for systems. In addi-
tion to the microcontroller core, it incorporates an
8–channel, 10–bit A/D converter with external refer-
ence so that its firmware can perform battery manage-
ment tasks without burdening the host CPU. A four–
channel 8–bit pulse–width modulator allows digital
control of functions such as LCD contrast and bright-
ness. An 8–bit port is provided for key scan inputs. A
total of 88 parallel I/O pins are available for key scan-
ning, system configuration, and power management
control.
The System Energy Manager scans a key matrix and
interfaces to the host CPU via an 8042–compatible port.
The benefits of sophisticated power management and
permanently powered functions are thereby attained
without adding to the system’s chip count.
Two 2–wire, bi–directional serial buses are incorpo-
rated to facilitate the management of slave peripheral
devices on the motherboard, such as digital tempera-
ture sensors and potentiometers, and to support exter-
nal low–speed I/O devices such as monitor configura-
tion channels, pen tablets, and joysticks.
Because a direct interface to the X–bus is provided, the
controller is not dependent on a particular core logic
chip or chip set. Independent chip select inputs for the
keyboard controller, power management #1, and power
management #2 registers are provided.
DS80CH11
011200 6/88
CONTROLLER BLOCK DIAGRAM Figure 1–1
VCC
P7.7 /
AMI.7 /
LED.7
CLK OSC.VPFW
VRST
GND
XTAL1XTAL2
PORT 7 /
ACT. MONITOR /
LED CONTROL
P7.0 /
AMI.0 /
LED.0
TIMING /
BUS CONTROL
ALE
PSEN
RST
P3.7 / RD
POR
P3.6 / WR
P3.5 / T1
P3.4 / T0
P3.3 / INT1
P3.2 / INT0
P3.1 / TXD0
P3.0 / RXD0
P1.7
POR
P1.6
P1.3 / SDA1
P1.2 / SCL1
P1.1 / T2EX
P1.0 / T2
P6.7 / SOC
POR
6 /
P6.6
P6.5 / PWI.1
P6.4 / PWI.0
P6.3 / PWO.3
P6.2 / PWO.2
P6.1 / PWO.1
P6.0 / PWO.0
PWM I/O
P1.5 / SDA2
P1.4 / SCL2
PORT 0PORT 2
PORT 4 /
KEYBOARD
PORT 8/
KEYBOARD
OUT
P0.7 /
AD7
P0.0 /
AD0
P2.7 /
A15
P2.0 /
P4.7 /
KSI.7
P4.0 /
KSI.0
P8.7/
KS0.7
P8.0/
KS0.0
P9.7/
KS0.15
P9.0/
KS0.8
POR
5 /
10–BIT
ADC
P5.0 / AI.0
P5.7 / AI.7
AGND
AVCC
VRL
VRH
PM1C
PC I/FuC I/F
KBC
PC I/F
uC I/F
KBC
OUTPUT
STATUS
KBCINPUTSD7–SD0
IOW
IOR
KBCS
KBOBF
SMI1
PM1CS
4 MHz
RING OSC.
SYS. CLOCKCONTROL
WATCHDOG
TIMER
TIMER 2
TIMER 1
TIMER 0
INT 1
INT 0
UART
ACC. BUS
SIO2
ACC. BUS
SIO1
SCRATCHPAD
REGISTERS
(256 BYTES)
POWER MON./
CONTROL
HVCC
HGND
SPECIAL
HIGH SPEED
256 x 8
FUNCTION
REGISTERS
80C520CPU CORE
DATA
RAM
POWERCONTROL
PORT 9/
KEYBOARD
OUT
P10.7
PORT 10
P10.0
PM1C
PM1C
PM2C
PC I/FuC I/F
PM2C
PM2C
STATUS
OUTPUT
INPUT
PM2CS
SMI2
STATUS
OUTPUT
INPUT
DS80CH11
011200 7/88
1.2DETAILED FEATURE SUMMARYHigh Speed 80C32 Compatible Core:High performance 4 clocks / machine cycle
(8032 = 12)Low Power: typically 1/3 power for equivalent
8032 throughputMaximum clock speed up to 25 MHz at 5.0VUltra–low stop mode power (typ. 1 uA) and
“IDLE” mode (typ. 10 mA)Multiple wake–up sources from STOP including
key scan, 2–wire, host I/F, or external interruptThree 16–bit timers, 1 serial port256 byte scratchpad256 bytes MOVX RAMKeyboard Control:Replaces 8042 and key scan microcontroller2 Parallel I/O ports for key scan outputsOne interrupt–driven 8–bit input port to initiate
key–scan sequenceInput/Output:Total of eleven 8–bit I/O ports; all pins can be
individually programmed to serve as general
purpose digital input/output.Each 8–bit port supports one or more special
functions:
Port 0, 2, 3: External program / data memory
interface
Port 1, 3: UART, 2–Wire serial, timers, and
external interrupt I/O.
Port 4, 8, 9: Key scan input / output
Port 5: A/D inputs
Port 6: PWM Outputs
Port 7: Activity monitor, LED Control
Port 10: GPIOAnalog Input/Output:Eight–channel, 10–bit A/D with power down
mode supports charging NiMH rechargeable
cells4–channel, 8–bit PWM supports LCD brightness
and contrast control2–Wire Bi–directional Serial BusesMaster/slave multi–drop operationManages on–board slaves or external I/O
devicesPower ControlGenerates system power on resetProgrammable power down pin states
1.3CONVENTIONS
The following conventions are used throughout this
specification:“SEM” is the short form name used to indicate the
System Energy Manager.Signals that are active low are followed by a pound
symbol (#) or backslash (\), or are indicated with an
overbar.If a range of signals is described, such as SA0 through
SA10, the range is given as SA10–0, with the most–
significant digit first and the least–significant digit last,
separated by a hyphen.Numbers written in this specification can be written as
decimal, hexadecimal, or binary. Hexadecimal num-
bers are followed by an “H” suffix. Binary numbers are
followed by a “B” suffix. For example, decimal
27 = 1BH = 00011011B.
1.4ADDITIONAL REFERENCES
The SEM incorporates the Dallas 8051 compatible High
Speed Micro core including the CPU and many of its
core peripherals. The operational details of these ele-
ments are contained in the Dallas High Speed Micro
User’s Guide.
DS80CH11
011200 8/88
2.0PIN DESCRIPTION
128–TQFP PIN ASSIGNMENT Figure 2–1
VRST
VPFW
P3.5 / T1
P3.4 / T0
P3.3 / INT1
P3.2 / INT0
P3.1 / TXD0
P3.0 / RXD0
P1.7
P1.6
P1.5 / SDA2
P1.4 / SCL2
P1.3 / SDA1
P1.2 / SCL1
P1.1 / T2EX
P1.0 / T2
GND
VCC
P4.7 / KSI.7
P4.6 / KSI.6
P4.5 / KSI.5
P4.4 / KSI.4
P4.3 / KSI.3
P4.2 / KSI.2
P4.1 / KSI.1
P4.0 / KSI.0
P7.7 / AMI.7 / LED.7
P7.6 / AMI.6 / LED.6
P7.5 / AMI.5 / LED.5
P7.4 / AMI.4 / LED.4
P7.3 / AMI.3 / LED.3
P7.2 / AMI.2 / LED.2
P7.1 / AMI.1 / LED.1
P7.0 / AMI.0 / LED.0
HVCC
P10.7
P10.6
P10.5
P9.7 / KSO.15
P9.6 / KSO.14
P9.5 / KSO.13
P9.4 / KSO.12
P9.3 / KSO.11
P9.2 / KSO.10
P9.1 / KSO.9
P9.0 / KSO.8
P8.7 / KSO.7
P8.6 / KSO.6
P8.5 / KSO.5
P8.4 / KSO.4
P8.3 / KSO.3
P8.2 / KSO.2
P8.1 / KSO.1
P8.0 / KSO.0
GND
VCC
P6.7 / SOC
P6.6
P6.5 / PWI.1
P6.4 / PWI.0
P6.3 / PWO.3
P6.2 / PWO.2
P6.1 / PWO.1
P6.0 / PWO.0
P5.7 / AI.7
P5.6 / AI.6
P5.5 / AI.5
P5.4 / AI.4
P5.3 / AI.3
P5.2 / AI.2
P5.1 / AI.1
P5.0 / AI.0
GND
IOW
IOR
SMI1
KBOBFPM1CS
KBCS
AGND
VRH
VRL
VCC
HGND
SD7SD6SD5SD4SD3SD2SD1SD0NC
SMI2
PM2CS
P10.0P10.1P10.2P10.3P10.4PSENALEP0.7 /
AD7
P0.6 /
AD6
P0.5 /
AD5
P0.4 /
AD4
P0.3 /
AD3
P0.2 /
AD2
P0.1 /
AD1
P0.0 /
AD0
VCCXT
AL2
AL1
GNDP2.7 /
A15
P2.6 /
A14
P2.5 /
A13
P2.4 /
A12
P2.3 /
P2.2 /
A10
P2.1 /
P2.0 /
RSTP3.7 / RDP3.6 / WR
10910810710610510410340414243444546474849505152535455565758596061626364
DS80CH11
011200 9/88
2.1PIN FUNCTION SUMMARY
PINSYMBOLDESCRIPTIONA0Command / Data Select: Input. Address input used by the host processor in data
transfers to the keyboard controller and power management #1 and #2 interface ports to
indicate whether the transfer is command (A0=1) or data (A0=0).AGNDAnalog Ground.
106ALEAddress Latch Enable: Output. This signal functions as a clock to latch the external
address LSB from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. ALE has a
pulse width of 1.5 XTAL1 cycles and a period of 4 XTAL1 cycles. ALE is forced high
when the SEM is in a Reset condition.AVCCAnalog VCC.
GNDDigital circuit ground.HGNDHost Interface Ground:HVCCHost Interface VCC:IORI/O Read: Input. I/O Read is used to signal a read operation is in effect on the host
address/data bus.IOWI/O Write: Input. I/O Write is used to signal a write operation is in effect on the host
address/data bus.KBCSKeyboard Chip Select: (Input, active low). This is a chip select signal used to enable
the keyboard control host interface port.KBOBFKeyboard Output Buffer Full: (Output, active high). This signal is set when the key-
board control host interface data buffer contains data to be read by the host. KBOBF will
be driven low when host reads the keyboard control data buffer register.
108No Connection.
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
Port 0 / Address/Data Outputs 7–0: I/O. Port 0 is an open–drain 8–bit bi–directional
I/O port. As an alternate function Port 0 can function as the multiplexed address/data
bus to access off–chip memory. During the time when ALE is high, the LSB of a memory
address is presented. When ALE falls to a logic 0, the port transitions to a bi–directional
data bus. This bus is used to read external ROM and read/write external RAM memory
or peripherals. When used as a memory bus, the port provides active high drivers. The
reset condition of Port 0 is tri–state. Pull–up resistors are required when using Port 0 as
an I/O port.
DS80CH11
011200 10/88
PINSYMBOLDESCRIPTION
P1.0 (T2)
P1.1 (T2EX)
P1.2 SCL1
P1.3 SDA1
P1.4 SCL2
P1.5 SDA2
P1.6
P1.7
Port 1/ (Alternate Functions): – I/O. Port 1 provides eight lines which can be individu-
ally selected as bi–directional I/O port pins or as the alternate functions listed below:
Alternate
PortFunctionDescription
P1.0T2External I/O for Timer/Counter 2
P1.1T2EXTimer/Counter 2 Capture/Reload Trigger
P1.2SCL12–Wire Serial Clock 1
P1.3SDA12–Wire Serial Data 1
P1.4SCL22–Wire Serial Clock 2
P1.5SDA22–Wire Serial Data 2
P1.6(None)
P1.7(None)
Note that P1.7 – P1.2 are high–drive pins which are always open–drain and must be
used with external pull–ups when used as I/O port pins. P1.1 and P1.0 have internal
pull–up resistors.
P2.0 (A8)
P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
Port 2 / Address Outputs A15–8: – I/O. Port 2 is a pseudo–bi–directional I/O port with
internal pull–up resistors. As an alternate function Port 2 can function as MSB of the
external address bus.
P3.0(RXD0)
P3.1 (TXD0)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0)
P3.5 (T1)
P3.6 (WR)
P3.7 (RD)
Port 3 / (Alternate Functions): – I/O. Port 3 provides eight lines each of which can
serve as psuedo–bi–directional I/O port pins or as the alternate functions as listed
below. Internal pull–up resistors are always present on these pins.
Alternate
PortFunctionDescription
P3.0RXD0Serial Port 0 Input
P3.1TXD0Serial Port 0 Output
P3.2INT0External Interrupt 0
P3.3INT1External Interrupt 1
P3.4T0Timer 0 External Input
P3.5T1Timer 1 External Input
P3.6WRExternal Data Memory Write Strobe
P3.7RDExternal Data Memory Read Strobe
P4.0 (KSI.0)
P4.1 (KSI.1)
P4.2 (KSI.2)
P4.3 (KSI.3)
P4.4 (KSI.4)
P4.5 (KSI.5)
P4.6 (KSI.6)
P4.7 (KSI.7)
Port 4 / KSI.7–0: – I/O / Keyboard Scan Inputs. Port 4 provides eight lines which can be
individually selected as psuedo–bi–directional I/O port pins or as an interrupt Inputs for
key scanning. Port 4 pins incorporate Schmitt inputs with pull–up resistors.
DS80CH11
011200 11/88
PINSYMBOLDESCRIPTION
P5.0 (AI.0)
P5.1 (AI.1)
P5.2 (AI.2)
P5.3 (AI.3)
P5.4 (AI.4)
P5.5 (AI.5)
P5.6 (AI.6)
P5.7 (AI.7)
Port 5 / AI.7–0: – I/O / A/D inputs. Port 5 provides eight lines which can be individually
selected as open–drain psuedo–bi–directional I/O port pins or as A/D inputs. Pull–up
resistors are required when using Port 5 as an I/O port.
P6.0 (PWO.0)
P6.1 (PWO.1)
P6.2 (PWO.2)
P6.3 (PWO.3)
P6.4 (PWI.0)
P6.5 (PWI.1)
P6.6
P6.7 / SOC
Port 6 / PW0.3 – 0: – I/O / Pulse–Width Modulated Outputs. Port 6 provides eight lines
which can all serve as psuedo–bi–directional I/O port pins with internal pull–up
resistors. Six lines can be individually selected to serve the pulse–width modulator
function indicated below:
Alternate
PortFunctionDescription
P6.0PWO.0PWM 0 output (active high drive when enabled)
P6.1PWO.1PWM 1 output (active high drive when enabled)
P6.2PWO.2PWM 2 output (active high drive when enabled)
P6.3PWO.3PWM 3 output (active high drive when enabled)
P6.4PWI.0Optional clock input for PWM channels 0 and 2
P6.5PWI.1Optional clock input for PWM channels 1 and 3
P6.6(none)
P6.7SOCExternal A / D start of conversion signal
P7.0 (AMI.0)
(LED.0)
P7.1 (AMI.1)
(LED.1)
P7.2 (AMI.2)
(LED.2)
P7.3 (AMI.3)
(LED.3)
P7.4 (AMI.4)
(LED.4)
P7.5 (AMI.5)
(LED.5)
P7.6 (AMI.6)
(LED.6)
P7.7 (AMI.7)
(LED.7)
Port 7 / AMI.7–0 / LED.7–0: – I/O / Activity Monitor Inputs / LED Control. Port 7 provides
eight lines which can serve as a psuedo–bi–directional I/O port pins with internal pull–
ups or as Activity Monitor inputs. When used as Activity Monitor inputs, these pins are
typically connected to the chip select line of an external peripheral device, and can be
programmed to sense active–high or active–low signals. Any pin which is programmed
as an Activity Monitor input by setting its AMEn bit to a 1 will have its pull–up device dis-
abled and thereby function as an open–drain pin in order to eliminate unnecessary cur-
rent drain. All port 7 pins are capable of controlling LED’s.
P8.0 (KSO.0)
P8.1 (KSO.1)
P8.2 (KSO.2)
P8.3 (KSO.3)
P8.4 (KSO.4)
P8.5 (KSO.5)
P8.6 (KSO.6)
P8.7 (KSO.7)
Port 8 / KSO.7–0:– I/O. Port 8 provides eight lines of open–drain psuedo–bi–directional
I/O port pins. Typically, these lines are used for key–scan outputs.
DS80CH11
011200 12/88
PINSYMBOLDESCRIPTION
P9.0 (KSO.8)
P9.1 (KSO.9)
P9.2 (KSO.10)
P9.3 (KSO.11)
P9.4 (KSO.12)
P9.5 (KSO.13)
P9.6 (KSO.14)
P9.7 (KSO.15)
Port 9 / KSO.15–8: – I/O. Port 9 provides eight lines of open–drain psuedo–bi–direc-
tional I/O port pins. Typically, these lines are used for key–scan outputs.
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
Port10: –I/O. Port 10 provides eight lines of general purpose Input or Output.PM1CSPower Management #1 Chip Select: (Input, active low). This is a chip select signal
used to enable the power management #1 host interface port.PM2CSPower Management #2 Chip Select: (Input, active low). This is a chip select signal
used to enable the power management #2 host interface port.
107PSENProgram Store Enable: Output. This signal goes low when off–chip program memory
is being accessed via Ports 0 and 2. It is commonly connected to optional external ROM
memory as a chip enable. PSEN will provide an active low pulse and is driven high when
external ROM is not being accessed.
105RSTReset: Input, active high The RST input pin contains a Schmitt voltage input to recog-
nize external active high Reset inputs. The pin also employs an internal pull–down
resistor to allow for a combination of wired OR external Reset sources. An RC is not
required for power–up, as the controller provides this function internally.
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
System Data Bus: (Bi–directional). SD7–0 are data bus lines used for data transfers
between the host processor and the keyboard interface buffer and power management
#1 and #2 interface buffers.SMI1System Management Interrupt #1: (Output, active low). This signal is driven low
when the power management #1 host interface data buffer contains data to be read by
the host. SMI1 will be returned to a High Level when host reads the power management
#1 data buffer register.SMI2System Management Interrupt #2: (Output, active low). This signal is driven low
when the power management #2, host interface data buffer contains data to be read by
the host. SMI2 will be returned to a high level when the host reads the power manage-
ment #2 data buffer register.
DS80CH11
011200 13/88
PINSYMBOLDESCRIPTION
VCCDigital Power Supply Input: For microcontroller and associated functions.
101VPFWPower Fail Warning: Output, active low. The VPFW pin signals an impending power
failure when VCC drops below VPFW voltage threshold.VRHA/D Positive Voltage Reference: The VRH pin is the positive reference (upper voltage
limit) of the A/D Converter.VRLA/D Negative Voltage Reference: The VRL pin is the negative reference (lower volt-
age limit) of the A/D Converter.
102VRSTPower Fail Reset: Output, active low. The VRST pin signals a “power not good” condi-
tion to the system when system VCC has dropped below the VRST voltage threshold.
XTAL1
XTAL2C Crystal Oscillator Inputs. XTAL1 and XTAL2 provide support for parallel resonant,
AT cut crystals. XTAL1 acts also as an input if there is an external clock source in place
of a crystal. XTAL2 serves as the output of the crystal amplifier.
DS80CH11
011200 14/88
2.2PIN CHARACTERISTICS
PINNAME
POWER DOWN
MODE STATEI/O BUFFER TYPE
RESET
STATEA0–I–AGND–––
106ALELowOLowAVCC–––GND–––GND–––GND–––
117GND–––HGND–––HVCC–––IOR–I–IOW–I–KBCS–I–KBOBFHoldOLowNC–––NC–––
108NC–––
121P0.0 / AD0High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
122P0.1 / AD1High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
123P0.2 / AD2High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
124P0.3 / AD3High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
125P0.4 / AD4High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
126P0.5 / AD5High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
127P0.6 / AD6High–ZOpen–Drain (port)
CMOS drive (bus)
High–Z
128P0.7 / AD7High–ZOpen–Drain (port)
CMOS drive (bus)
High–ZP1.0 / T2HoldPull–upWeak HighP1.1 / T2EXHoldPull–upWeak HighP1.2 / SCL1HoldOpen–drainHigh–ZP1.3 / SDA1HoldOpen–drainHigh–Z
DS80CH11
011200 15/88
2.2 PIN CHARACTERISTICS (cont’d)
PINNAME
POWER DOWN
MODE STATEI/O BUFFER TYPE
RESET
STATEP1.4 /SCL2HoldOpen–drainHigh–ZP1.5 /SDA2HoldOpen–drainHigh–ZP1.6HoldOpen–drainHigh–ZP1.7HoldOpen–drainHigh–Z
109P2.0 / A8HoldPull–upWeak High
110P2.1 / A9HoldPull–upWeak High
111P2.2 / A10HoldPull–upWeak High
112P2.3 / A11HoldPull–upWeak High
113P2.4 / A12HoldPull–upWeak High
114P2.5 / A13HoldPull–upWeak High
115P2.6 / A14HoldPull–upWeak High
116P2.7 / A15HoldPull–upWeak HighP3.0 / RXD0HoldPull–upWeak HighP3.1 / TXD0HoldPull–upWeak HighP3.2 / INT0HoldPull–upWeak HighP3.3 / INT1HoldPull–upWeak HighP3.4 / T0HoldPull–upWeak High
100P3.5 / T1HoldPull–upWeak High
103P3.6 / WRHoldPull–upWeak High
104P3.7 / RDHoldPull–upWeak HighP4.0 / KSI.0HoldPull–upWeak HighP4.1 / KSI.1HoldPull–upWeak HighP4.2 / KSI.2HoldPull–upWeak HighP4.3 / KSI.3HoldPull–upWeak HighP4.4 / KSI.4HoldPull–upWeak HighP4.5 / KSI.5HoldPull–upWeak HighP4.6 / KSI.6HoldPull–upWeak HighP4.7 / KSI.7HoldPull–upWeak HighP5.0 / AI.0HoldOpen–drainHigh–ZP5.1 / AI.1HoldOpen–drainHigh–ZP5.2 / AI.2HoldOpen–drainHigh–ZP5.3 / AI.3HoldOpen–drainHigh–Z
DS80CH11
011200 16/88
2.2 PIN CHARACTERISTICS (cont’d)
PINNAME
POWER DOWN
MODE STATEI/O BUFFER TYPE
RESET
STATEP5.4 / AI.4HoldOpen–drainHigh–ZP5.5 / AI.5HoldOpen–drainHigh–ZP5.6 / AI.6HoldOpen–drainHigh–ZP5.7 / AI.7HoldOpen–drainHigh–ZP6.0 / PWO.0HoldPull–up (PWMn disabled)
CMOS drive (PWMn enabled)
Weak HighP6.1 / PWO.1HoldPull–up (PWMn disabled)
CMOS drive (PWMn enabled)
Weak HighP6.2 / PWO.2HoldPull–up (PWMn disabled)
CMOS drive (PWMn enabled)
Weak HighP6.3 / PWO.3HoldPull–up (PWMn disabled)
CMOS drive (PWMn enabled)
Weak HighP6.4 / PWI.0HoldPull–upWeak HighP6.5 / PWI.1HoldPull–upWeak HighP6.6HoldPull–upWeak HighP6.7 / SOCHoldPull–upWeak HighP7.0 / AMI.0 /
LED.0
HoldPull–upWeak HighP7.1 / AMI.1 /
LED.1
HoldPull–upWeak HighP7.2 / AMI.2 /
LED.2
HoldPull–upWeak HighP7.3 / AMI.3 /
LED.3
HoldPull–upWeak HighP7.4 / AMI.4/
LED.4
HoldPull–upWeak HighP7.5 / AMI.5/
LED.5
HoldPull–upWeak HighP7.6 / AMI.6/
LED.6
HoldPull–upWeak HighP7.7 / AMI.7/
LED.7
HoldPull–upWeak HighP8.0 / KSO.0HoldOpen–drainHigh–ZP8.1 / KSO.1HoldOpen–drainHigh–ZP8.2 / KSO.2HoldOpen–drainHigh–ZP8.3 / KSO.3HoldOpen–drainHigh–ZP8.4 / KSO.4HoldOpen–drainHigh–ZP8.5 / KSO.5HoldOpen–drainHigh–ZP8.6 / KSO.6HoldOpen–drainHigh–Z
DS80CH11
011200 17/88
2.2 PIN CHARACTERISTICS (cont’d)
PINNAME
POWER DOWN
MODE STATEI/O BUFFER TYPE
RESET
STATEP8.7 / KSO.7HoldOpen–drainHigh–ZP9.0 / KSO.8HoldOpen–drainHigh–ZP9.1 / KSO.9HoldOpen–drainHigh–ZP9.2 / KSO.10HoldOpen–drainHigh–ZP9.3 / KSO.11HoldOpen–drainHigh–ZP9.4 / KSO.12HoldOpen–drainHigh–ZP9.5 / KSO.13HoldOpen–drainHigh–ZP9.6 / KSO.14HoldOpen–drainHigh–ZP9.7 / KSO.15HoldOpen–drainHigh–ZP10.0HoldPull–upWeak HighP10.1HoldPull–upWeak HighP10.2HoldPull–upWeak HighP10.3HoldPull–upWeak HighP10.4HoldPull–upWeak HighP10.5HoldPull–upWeak HighP10.6HoldPull–upWeak HighP10.7HoldPull–upWeak HighPM1CS–I–PM2CS–I–
107PSENLowOLow
105RST–I–SD0(note 2)Bi–directional(note 2)SD1(note 2)Bi–directional(note 2)SD2(note 2)Bi–directional(note 2)SD3(note 2)Bi–directional(note 2)SD4(note 2)Bi–directional(note 2)SD5(note 2)Bi–directional(note 2)SD6(note 2)Bi–directional(note 2)SD7(note 2)Bi–directional(note 2)SMI1HoldOHighSMI2HoldOHighVCC–––VCC–––
120VCC–––
DS80CH11
011200 18/88
2.2 PIN CHARACTERISTICS (cont’d)
PINNAME
POWER DOWN
MODE STATEI/O BUFFER TYPE
RESET
STATE
101VPFW(note 3)O(note 3)VRH–––VRL–––
102VRST(note 3)O(note 3)
118XTAL1–I–
119XTAL2HO–
PIN STATE DESCRIPTIONS
High–ZHigh Impedance
EnabledPower applied; electrically functioning input
UnchangedPrevious state not affected
NOTES:As shown above, the original port pins P1.7–P1.2 have been modified to open–drain instead of having “Internal”
pull–up resistors.This signal is independently powered from the HVCC on pin 68. As a result, the state of the reset pin and the power
down mode have no effect on its operation.VRST and VPFW reflects the state of VCC with respect to the power–fail reset and power–fail warning trip points,
respectively, and is unaffected by the RST pin and power down mode state.
DS80CH11
011200 19/88
3.0CORE MICROCONTROLLER
3.1CORE MICRO OVERVIEW
The SEM incorporates the Dallas High Speed Micro
core which is a fully static CMOS 8051 compatible
microcontroller with a new internal architecture
designed for high performance. The higher speed
operation of the microcontroller core comes not just
from increasing the clock frequency, but from a newer,
more efficient design of the internal architecture. The
major features of the High Speed Micro Core include:4 clocks/machine cycle (8032 = 12)Wasted cycles removedRuns DC to 25 Mhz clock rates @ 5VSingle–cycle instruction in 160 nsUses less power for equivalent workDual data pointerOptional variable length MOVX to access fast/slow
RAM /peripherals
3.2INSTRUCTION SET SUMMARY
All instructions in the SEM perform the same functions
as their 80C32 counterparts. Their affect on bits, flags,
and other status functions are identical. However, the
timing of each instruction is different. This applies both
in absolute and relative number of clocks.
For absolute timing of real–time events, the timing of
software loops will need to be calculated using the table
below. However, counter/timers default to run at the
older 12 clocks per increment. Therefore, while soft-
ware runs at higher speed, timer–based events need no
modification to operate as before. Timers can be set to
run at 4 clocks per increment cycle to take advantage of
higher speed operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @ DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the GEM, the
MOVX instruction can be done in two machine cycles or
8 oscillator cycles but the “MOV direct, direct” uses
three machine cycles or 12 oscillator cycles. While both
are faster than their original counterparts, they now
have different execution times from each other. This is
because in most cases, the SEM uses one cycle for
each byte. The timing of each instruction should be
examined for familiarity with the changes. Note that a
machine cycle now requires just four clocks, and pro-
vides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the orig-
inal architecture, all were one or two cycles except for
MUL and DIV.
INSTRUCTION SET SUMMARY Table 3–1
Legends:–Accumulator–Register R7–R0
direct–Internal Register address
@Ri–Internal Register pointed–to by R0 or R1
(except MOVX)
rel–2’s complement offset byte
bit–direct bit–address
#data–8–bit constant
#data 16–16–bit constant
addr 16–16–bit destination address
addr 11–11–bit destination address
DS80CH11
011200 20/88
INSTRUCTION SET SUMMARY Table 3–1 (cont’d)
INSTRUCTIONBYTE
OSCILLATOR
CYCLESINSTRUCTIONBYTE
OSCILLATOR
CYCLES
Arithmetic Instructions:
ADD A, Rn14INC A14
ADD A, direct28INC Rn14
ADD A, @Ri14INC direct28
ADD A, #data28INC @Ri14
ADDC A, Rn14INC DPTR112
ADDC A, direct28DEC A14
ADDC A, @Ri14DEC Rn14
ADDC A, #data28DEC direct28
SUBB A, Rn14DEC @Ri14
SUBB A, direct28MUL AB120
SUBB A, @Ri14DIV AB120
SUBB A, #data28DA A14
Logical Instructions:
ANL A, Rn14XRL A, Rn14
ANL A, direct28XRL A, direct28
ANL A, @Ri14XRL A, @Ri14
ANL A, #data28XRL A, #data28
ANL direct, A28XRL direct, A28
ANL direct, #data312XRL direct, #data312
ORL A, Rn14CLR A14
ORL A, direct28CPL A14
ORL A, @Ri14RL A14
ORL A, #data28RLC A14
ORL direct, A28RR A14
ORL direct, #data312RRC A14
SWAP A14
Data Transfer
Instructions:
MOV A, Rn14MOVC A, @A+DPTR112
MOV A, direct28MOVC A, @A+PC112
MOV A, @Ri14MOVX A, @Ri18–36
MOV A, #data28MOVX A, @DPTR18–36
MOV Rn, A14MOVX @Ri, A18–36
MOV Rn, direct28MOVX @DPTR, A18–36
MOV Rn, #data28PUSH direct28
MOV direct, A28POP direct28
MOV direct, Rn28XCH A, Rn14
MOV direct1, direct2312XCH A, direct28
MOV direct, @Ri28XCH A, @Ri14
MOV direct, #data312XCHD A, @Ri14
MOV @Ri, A14
MOV @Ri, direct28
MOV @Ri, #data28
MOV DPTR, #data 16312
DS80CH11
011200 21/88
INSTRUCTION SET SUMMARY Table 3–1 (cont’d)
Bit Manipulation
Instructions:
CLR C14ANL C, bit28
CLR bit28ANL C, bit28
SETB C14ORL C, bit28
SETB bit28ORL C, bit28
CPL C14MOV C, bit28
CPL bit28MOV bit, C28
Program Branching
Instructions:
ACALL addr 11212CJNE A, direct, rel316
LCALL addr 16316CJNE A, #data, rel316
RET116CJNE Rn, #data, rel316
RETI116CJNE @ Ri, #data, rel316
AJMP addr 11212NOP14
LJMP addr 16316JC rel212
SJMP rel212JNC rel212
JMP @A+DPTR112JB bit, rel316
JZ rel212JNB bit, rel316
JNZ rel212JBC bit, rel316
DJNZ Rn, rel212
DJNZ direct, rel316
The Table above shows the speed for each class of
instruction. Note that many of the instructions have mul-
tiple opcodes. There are 255 opcodes for 111 instruc-
tions. Of the 255 opcodes, 159 are three times faster
than the original 80C32. While a system than empha-
sizes those instructions will see the most improvement,
the large total number that receive a three to one
improvement assure a dramatic speed increase for any
system. The speed improvement summary is provided
below.
3.3SPEED IMPROVEMENT
The following table summarizes the speed improve-
ment of the High Speed Micro core over a standard 12
clock / machine cycle 8052 device.
#OpcodesSpeed Improvement
1593.0 x1.5 x2.0 x2.4 x
255Average:2.5
3.4INSTRUCTION SET ADDITIONAL
REFERENCES
The user should refer to the Dallas High Speed Micro
User’s Guide for a complete description of the instruc-
tion set including its address modes, coding, and timing
for the SEM.
3.5RESET
The High–Speed Micro has three ways of entering a
reset state:Power–On / Fail ResetWatchdog Timer ResetExternal Reset
The operation of the CPU timing and states during a
reset are documented in the Dallas High Speed Micro
User’s Guide under the “Reset Conditions” section. The
Watchdog Timer reset is documented in the Watchdog
Timer section of the Dallas High Speed Micro User’s
Guide. The operation of the Power–On / Fail reset is
described in the Power Management section of this doc-
ument.
DS80CH11
011200 22/88
3.6INTERRUPT CONTROL
The SEM provides 16 sources of interrupt with three
priority levels. The Power–fail Interrupt (PFI), if
enabled, always has the highest priority. There are two
remaining user selectable priorities: high and low. If two
interrupts that have the same priority occur simulta-
neously, the hardware–determined precedence given
below determines which is a acted upon. Except for the
PFI, all interrupts that are new to the 8051 family have a
lower natural priority than the originals.
INTERRUPT PRIORITY Table 3–2
NAMEDESCRIPTIONVECTOR
NATURAL
PRIORITY8051/DALLAS
PFIPower Fail Interrupt33h1DALLAS
INT0External Interrupt 003h28051
TF0Timer 00Bh38051
INT1External Interrupt 113h48051
TF1Timer 11Bh58051
SCON0TI0 or RI0 from Serial Port 023h68051
TF2Timer 22Bh78051
AMIActivity Monitor Interrupt3Bh8DALLAS
2WI12–Wire Serial Port 143h9DALLAS
ADIA/D End of Conversion4Bh10DALLAS
2WI22–Wire Serial Port 253h11DALLAS
KBIKeyboard Buffer Input5Bh12DALLAS
PBI1Power Mgmt. Buffer Input #163h13DALLAS
KDIKey Detect Input6Bh14DALLAS
WDIWatchDog Periodic Interrupt73h15DALLAS
PBI2Power Mgmt. Buffer Input #27Bh16DALLAS
INTERRUPT CONTROL SUMMARY Table 3–3
INTERRUPT
SOURCEFLAG(S)
FLAG
LOC.ENABLE
ENABLE
LOC.PRIORITY
PRIORITY
LOC.
Power FailPFIWDCON.4EPFIWDCON.5N/AN/A
External 0IE0TCON.1EX0IE.0PX0IP.0
Timer 0TF0TCON.5ET0IE.1PT0IP.1
External 1IE1TCON.3EX1IE.2PX1IP.2
Timer 1TF1TCON.7ET1IE.3PT1IP.3
Serial Port 0RI0,TI0SCON0.0/
SCON0.1
ES0IE.4PS0IP.4
Timer 2TF2T2CON.7ET2IE.5PT2IP.5
Activity monitorAMF7–0AMF.7–0EAMIE.6PAMIP.6
DS80CH11
011200 23/88
INTERRUPT CONTROL SUMMARY Table 3–3 (cont’d)
INTERRUPT
SOURCEFLAG(S)
FLAG
LOC.ENABLE
ENABLE
LOC.PRIORITY
PRIORITY
LOC.
2–Wire Serial Port 12WIF12WCON1.4E2W1EIE.0P2W1EIP.0
A/D End of Conv.EOCADCON1.6EADEIE.1PADEIP.1
2–Wire Serial Port 22WIF22WCON2.4E2W2EIE.2P2W2EIP.2
Keyboard BufferKIBFKBSTAT.1EKBEIE.3PKBEIP.3
Power Mgmt. #1 BufferPIBF1PMSTAT1.1EPB1EIE.4PPB1EIP.4
Key Detect InputKDF7–0KDF.7–0EKDEIE.5PKDEIP.5
WatchDog periodicWDIFWDCON.3EWDIEIE.6PWDIEIP.6
Power Mgmt. #2 BufferPIBF2PMSTAT2.1EPB2EIE.7PPB2EIP.7
A complete description of the interrupt structure of the microcontroller core including operation of the priority scheme
and acknowledgment operation is contained in the Dallas High Speed Micro User’s Guide.
DS80CH11
011200 24/88
4.0MEMORY RESOURCES
4.1OVERVIEW
The SEM contains the following memory resources and
features:256 bytes of on–chip direct (scratchpad) RAM256 bytes of on–chip MOVX data RAMOff–chip program and data memory expansionSoftware enable/disable of on–chip data memory
4.2DATA MEMORY ACCESS
Unlike many 8051 derivatives, the SEM contains on–
chip data memory. Although physically on–chip, soft-
ware accesses this area in the same way off–chip data
memory is accessed: via the MOVX instruction. The
256 bytes of SRAM is located between address 0000h
and 00FFh.
Access to the on–chip data RAM is optional under soft-
ware control. When enabled by software, the data
SRAM is between 0000h and 00FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 256
automatically go to external memory through Ports
0 & 2.
When disabled, the 256 bytes of memory area is trans-
parent to the system memory map. Any MOVX directed
to the space between 0000h and FFFFh goes to the
expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the SEM to drop into an
existing system that uses these addresses for other
hardware and still have full compatibility.
The on–chip data area is selected by software using two
bits in the Power Management Register at location C4h.
This selection is dynamically programmable. Thus
access to the on–chip area becomes transparent to
reach off–chip devices at the same addresses. The
control bits are DME1 (PMR.1) and DME0 (PMR.0).
Their operation is described in Table 4–1.
DATA MEMORY ACCESS CONTROL Table 4–1
DME1DME0DATA MEMORY ADDRESSMEMORY FUNCTION00000h – FFFFhExternal Data Memory (Default condition)10000h – 00FFh
0100h – FFFFh
Internal SRAM Data Memory
External Data Memory0ReservedReserved10000h – 00FFh
0100h – FFFBh
FFFCh
FFFDh – FFFFh
Internal SRAM Data Memory
Reserved – no external access
Read access to the status of lock bits
Reserved – no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security
lock bits LB3–LB1. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read
only.
4.2.1Stretch Memory Cycle
The SEM allows software to adjust the speed of off–chip
data memory access. The micro is capable of perform-
ing the MOVX in as little as two instruction cycles. The
on–chip SRAM uses this speed and any MOVX instruc-
tion directed internally uses two cycles. However, the
time can be stretched for interface to external devices.
This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high–
speed systems, it may not be necessary or desirable to
perform off–chip data memory access at full speed. In
addition, there are a variety of memory mapped periph-
erals such as LCDs or UARTs that are slow.
Operation of the Stretch MOVX function is fully docu-
mented in the Dallas High Speed Micro User’s Guide.
DS80CH11
011200 25/88
4.2.2Dual Data Pointer
A second data pointer register (DPTR 1) is incorporated
into the SEM in addition to the standard one in the 8051.
This feature allows faster execution of many operations
involving data memory access, such as block moves.
Operation of the dual data pointer function is fully docu-
mented in the Dallas High Speed Micro User’s Guide.
4.3EXTERNAL MEMORY INTERFACE
Interface techniques for interfacing external memory as
program or data storage to the SEM via Ports 0 and 2
are described in the Dallas High Speed Micro User’s
Guide.
4.4DIRECT (SCRATCHPAD) RAM ACCESS
The SEM incorporates a full 256 bytes of direct RAM.
This RAM is accessed in a manner identical to that of a
standard 80C52 compatible device. A full description of
this memory along with the instructions that access it is
contained in the Dallas High Speed Micro User’s Guide.
4.5SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special
features of the SEM. This allows the SEM to have many
new features but use the same instruction set as the
8051. When writing software to use a new feature, an
equate statement defines the SFR to an assembler or
compiler. This is the only change needed to access the
new function. The SEM duplicates the SFRs contained
in the standard 80C52. Table 4–2 is a summary of the
values loaded into the SEM’s SFR’s on reset. Table 4–3
is a summary of all of the SFR’s and the control bits they
contain.
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
DS80CH11
011200 26/88
SPECIAL FUNCTION REGISTER RESET VALUES Table 4–2
* New functions are in bold
EIP
00000000
PORT10
PMSTAT2
XXXXXX00
PMDIN2
XXXXXXXX
PMDOUT2
XXXXXXXX
EIE
PORT9
PW23CON
PWM2
PWM3
00000000
ACC
PORT8
PW23CS
PW2FG
PW3FG
WDCON
0X0X0XX0
2WCON2
2WSTAT12
2WSTAT22
PW01CON
PWM0
PWM1
00000000
PSW
2WSADR2
2WDAT2
2WFS2
PORT7
PW01CS
PW0FG
PW1FG
00000000
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PMR
010X0000
STATUS
11111111
SADEN0
PORT6
PMSTAT1
XXXXXX00
PMDIN1
XXXXXXXX
PMDOUT1
XXXXXXXX
PORT3
ADCON1
ADCON2
ADMSB
ADLSB
WINHI
WINLO
00000000
SADDR0
PORT5
KBSTAT
XXXXXX00
KBDIN
XXXXXXXX
KBDOUT
XXXXXXXX
PORT2
PORT4
KDE
KDF
00000000
SCON0
SBUF0
2WSADR1
2WDAT1
2WFS1
2WCON1
2WSTAT11
2WSTAT21
00000000
PORT1
EXIF
0000XXX0
AME
AMQ
AMP
AMF
00000000
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
00000001
PORT0
DPL
DPH
DPL1
DPH1
DPS
00000000
PCON
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
DS80CH11
011200 27/88
SPECIAL FUNCTION REGISTER LOCATIONS Table 4–3
* New functions are in bold
REGISTERBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0ADDRESS
PORT0P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.080h81h
DPL82h
DPH83h
DPL184h
DPH185h
DPS0000000SEL86h
PCONSMODSMOD0––GF1GF0STOPIDLE87h
TCONTF1TR1TF0TR0IE1IT1IE0IT088h
TMODGATEC/TM1M0GATEC/TM1M089h
TL08Ah
TL18Bh
TH08Ch
TH18Dh
CKCONWD1WD0T2MT1MT0MMD2MD1MD08Eh
PORT1P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.090h
EXIF––––XT/RGRGMDRGSLBGS91h
AMEAME7AME6AME5AME4AME3AME2AME1AME092h
AMQAMQ7AMQ6AMQ5AMQ4AMQ3AMQ2AMQ1AMQ093h
AMPAMP7AMP6AMP5AMP4AMP3AMP2AMP1AMP094h
AMFAMF7AMF6AMF5AMF4AMF3AMF2AMF1AMF095h
SCON0SM0/FESM1SM2RENTB8RB8TI0RI098h
SBUF0SB7SB6SB5SB4SB3SB2SB1SB099h
2WSADR1SLA6SLA5SLA4SLA3SLA2SLA1SLA0–9Ah
2WDAT19Bh
2WFS19Ch
2WCON12WEN1STA1STO12WIF1BMM1ANAK1––9Dh
2WSTAT11BER1ARL1RSTO1TXI1RXI1TSTA1RSTA1–9Eh
2WSTAT21BB1ADM1X/R1ACKS1––––9Fh
PORT2P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0A0h
PORT4P4.7P4.6P4.5P4.4P4.3P4.2P4.1P4.0A4h
KDEKDE7KDE6KDE5KDE4KDE3KDE2KDE1KDE0A5h
KDFKDF7KDF6KDF5KDF4KDF3KDF2KDF1KDF0A6hEAEAMET2ES0ET1EX1ET0EX0A8h
SADDR0A9h
DS80CH11
011200 28/88
SPECIAL FUNCTION REGISTER LOCATIONS Table 4–3 (cont’d)
* New functions are in bold
REGISTERBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0ADDRESS
PORT5P5.7P5.6P5.5P5.4P5.3P5.2P5.1P5.0ACh
KBSTATKST7KST6KST5KST4KC/DKST2KIBFKOBFADh
KBDINAEh
KBDOUTAFh
PORT3P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0B0h
ADCON1STRT/
BSY
EOCCONT/
ADEXWCQWCMADONWCIOB2h
ADCON2OUTCFMUX2MUX1MUX0APS3APS2APS1APS0B3h
ADMSBADC9/
ADC8/
ADC7/
ADC6/
ADC5/
ADC4/
ADC3/
ADC9
ADC2/
ADC8B4h
ADLSBADC7ADC6ADC5ADC4ADC3ADC2ADC1ADC0B5h
WINHIB6h
WINLOB7h–PAMPT2PS0PT1PX1PT0PX0B8h
SADEN0B9h
PORT6P6.7P6.6P6.5P6.4P6.3P6.2P6.1P6.0BCh
PMSTAT1P1ST7P1ST6P1ST5P1ST4PC/D1P1ST2PIBF1POBF1BDh
PMDIN1BEh
PMDOUT1BFh
PMRCD1CD0SWB–XTOFFALE-
OFF
DME1DME0C4h
STATUSPIPHIPLIPXTUP––SPTA0SPRA0C5hC7h
T2CONTF2EXF2RCLKTCLKEXEN2TR2C/T2CP/
RL2
C8h
T2MOD––––––T2OEDCENC9h
RCAP2LCAh
RCAP2HCBh
TL2CCh
TH2CDh
PSWCYACF0RS1RS0OVFLPD0h
2WSADR2SLA6SLA5SLA4SLA3SLA2SLA1SLA0–D1h
2WDAT2––––––––D2h
2WFS2D3h
PORT7P7.7P7.6P7.5P7.4P7.3P7.2P7.1P7.0D4h
DS80CH11
011200 29/88
SPECIAL FUNCTION REGISTER LOCATIONS Table 4–3 (cont’d)
* New functions are in bold
REGISTERBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0ADDRESS
PW01CSPW0S2PW0S1PW0S0PW0ENPW1S2PW1S1PW1S0PW1END5h
PW0FGD6h
PW1FGD7h
WDCONSMODPOREPFIPFIWDIFWTRFEWTRWTD8h
2WCON22WEN2STA2STO22WIF2BMM2ANAK2––D9h
2WSTAT12BER2ARL2RSTO2TXI2RXI2TSTA2RSTA2–DAh
2WSTAT22BB2ADM2X/R2ACKS2––––DBh
PW01CONPW0
PW0
PW0
PW0
T/C
PW1
PW1
PW1
PW1
T/C
DDh
PWM0DEh
PWM1DFh
ACCE0h
PORT8P8.7P8.6P8.5P8.4P8.3P8.2P8.1P8.0E4h
PW23CSPW2S2PW2S1PW2S0PW2ENPW3S2PW3S1PW3S0PW3ENE5h
PW2FGE6h
PW3FGE7h
EIEEPB2EWDIEKDEPB1EKBE2W2EADE2W1E8h
PORT9P9.7P9.6P9.5P9.4P9.3P9.2P9.1P9.0ECh
PW23CONPW2
PW2
PW2
PW2
T/C
PW3
PW3
PW3
PW3
T/C
EDh
PWM2EEh
PWM3EFhF0h
PORT10P10.7P10.6P10.5P10.4P10.3P10.2P10.1P10.0F4h
PMSTAT2P2ST7P2ST6P2ST5P2ST4PC/D2P2ST2PIBF2POBF2F5h
PMDIN2F6h
PMDOUT2F7h
EIPPPB2PWDIPKDPPB1PKBP2W2PADP2W1F8h
DS80CH11
011200 30/88
5.0CORE I/O RESOURCES
The SEM incorporates a full complement of the
80C52–compatible I/O resources as well as a number of
specialized I/O resources which are associated with the
Dallas High–Speed micro core. These features are
described in this section.
5.1PROGRAMMABLE TIMERS
Three programmable timers are included which are
compatible with the standard 80C52. All of the functions
are duplicated and all of the control bits and registers
associated with these functions are in their standard
locations. The standard operating modes of each timer
are fully described in the Dallas High Speed Micro
User’s Guide.
There is one important difference between the Dallas
High Speed Micro Core and the 8051 regarding timers.
The original 8051 used 12 clocks per cycle for timers as
well as for machine cycles. The High Speed Micro archi-
tecture normally uses 4 clocks per machine cycle. How-
ever, in the area of timers and serial port, the High
Speed Micro will default to 12 clocks per cycle on reset.
This allows existing code with real–time dependencies
such as baud rates to operate properly.
If an application needs higher speed timers or serial
baud rates, the user can select individual timers to run at
the 4 clock rate. The Clock Control register (CKCON;
8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the High Speed Micro core uses
4 clocks per cycle to generate timer speeds. When the
bit is a 0, the High Speed Micro core uses 12 clocks for
timer speeds. The reset condition is a 0. CKCON.5
selects the speed of Timer 2. CKCON.4 selects Timer 1
and CKCON.3 selects Timer 0. Note that unless a user
desires very fast timing, it is unnecessary to alter these
bits. Note that the timer controls are independent.
5.2SERIAL PORT
The SEM provides a serial port (UART) that is identical
to the 80C52. The duplicate serial port implemented as
described in the Dallas High Speed Micro User’s Guide
is not present. Operation of the original serial port,
which is called Serial Port 0, is fully described in the
User’s Guide.
5.3WATCHDOG TIMER
To prevent software from losing control, the SEM
includes a programmable Watchdog Timer. The Watch-
dog is a free running timer that sets a flag if allowed to
reach a preselected time–out. It can be (re)started by
software.
A typical application is to select the flag as a reset
source. When the Watchdog times out, it sets its flag
which generates reset. Software must restart the timer
before it reaches its time–out or the processor is reset.
Software can select one of four time–out values. Then, it
restarts the timer and enables the reset function. After
enabling the reset function, software must then restart
the timer before its expiration or hardware will reset the
CPU. Both the Watchdog Reset Enable and the Watch-
dog Restart control bits are protected by a “Timed
Access” circuit. This prevents errant software from acci-
dentally clearing the Watchdog. Time–out values are
precise since they are a function of the crystal frequency
as shown below in Table 5–1. For reference, the time
periods at 25 MHz also are shown.
The Watchdog also provides a useful option for systems
that do not require a reset circuit. It will set an interrupt
flag 512 clocks before setting the reset flag. Software
can optionally enable this interrupt source. The interrupt
is independent of the reset. A common use of the inter-
rupt is during debug, to show developers where the
Watchdog times out. This indicates where Watchdog
must be restarted by software. The interrupt also can
serve as a convenient time–base generator or can
wake–up the processor.
The Watchdog function is controlled by the Clock Con-
trol (CKCON – 8Eh), Watchdog Control (WDCON –
D8h), and Extended Interrupt Enable (EIE – E8h) SFRs.
CKCON.7 and CKCON.6 are WD1 and WD0 respec-
tively and they select the Watchdog time–out period as
shown in Table 5–1. A complete operational description
for the Watchdog Timer is given in the Dallas High
Speed Micro User’s Guide.
DS80CH11
011200 31/88
WATCHDOG TIMER INTERRUPT / RESET TIMEOUT VALUES Table 5–1
WD1WD0
INTERRUPT
TIME–OUTTIME (25 MHz)
RESET
TIME–OUTTIME (25 MHz)0217 clocks5.243 ms217 + 512 clocks5.263 ms1220 clocks41.94 ms220 + 512 clocks41.96 ms0223 clocks335.54 ms223 + 512 clocks335.56 ms1226 clocks2684.35 ms226 + 512 clocks2684.38 ms
5.4PARALLEL I/O PORTS
The SEM incorporates the original four pseudo–bi–
directional parallel I/O ports found in the 80C52: Ports
0, 1, 2 and 3. All of these ports operate logically as docu-
mented in the Dallas High Speed Micro User’s Guide.
All of the Port 0, 1, 2, and 3 pins exhibit the same electri-
cal characteristics as documented in the user’s guide
except for P1.7 – P1.2 which are open–drain pins.
In addition to these basic ports, the SEM adds an addi-
tional seven 8–bit ports. All of these additional ports
incorporate the same logical I/O structure as the original
four, Ports 0 through 3. Therefore, they are pro-
grammed the same as Ports 0–3. The SFR addresses
for the new ports are as follows:
Port 4:0A4H
Port 5:0ACH
Port 6:0BCH
Port 7:0D4H
Port 8:0E4H
Port 9:0ECH
Port 10:0F4H
5.4.1Alternate Pin Function Summary
A number of port pins on the SEM offer an optional alter-
nate function. These functions are individually select-
able; i.e. each pin can be programmed for use as a gen-
eral purpose I/O or to serve the alternate function. In
order to use the alternate function, the associated port
latch must be programmed to a 1. The alternate func-
tions are summarized in Table 5–2 below.
PORT PIN ALTERNATE FUNCTIONS Table 5–2
PIN(S)
ALTERNATE
PIN(S)ALTERNATE FUNCTION(S)
P0.7 – P0.0AD7 – AD0Mux. addr. / data bus
P1.7–None
P1.6–None
P1.5SDA22–Wire Serial Port Data Input/Output 2
P1.4SCL22–Wire Serial Port Clock 2
P1.3SDA12–Wire serial port data Input / Output 1
P1.2SCL12–Wire serial port clock 1
P1.1T2EXTimer 2 capture / reload input
P1.0T2Timer 2 output pulse
P2.7 – P2.0A15 – A8Address bus outputs
P3.7RDRead strobe output
P3.6WRWrite strobe output
P3.5T1Timer 1 input
P3.4T0Timer 0 input
P3.3INT1External interrupt 1 input (active low)
P3.2INT0External interrupt 0 input (active low)
P3.1TXD0UART Transmit
DS80CH11
011200 32/88
PORT PIN ALTERNATE FUNCTIONS Table 5–2 (cont’d)
P3.0RXD0UART Receive
P4.7 – P4.0KSI.7 – KSI.0Keyboard scan inputs
P5.7 – P5.0AI.7 – AI.0A/D analog inputs
P6.7SOCA/D start of conversion input
P6.6–(None)
P6.5 – P6.4PWI.1 – PWI.0PWM channels 1 and 0 inputs
P6.3 – P6.0PWO.3 – PWO.0PWM channels 3, 2, 1, and 0 outputs
P7.7 – P7.0AMI.7 – AMI.0
LED.7 –LED.0
Activity monitor inputs /
LED Control
P8.7 – P8.0KSO.7 – KSO.0Keyboard Scan Outputs
P9.7 – P9.0KSO.15 – KSO.8Keyboard Scan Outputs
P10.7 – P10.0–(None)
DS80CH11
011200 33/88
6.02–WIRE SERIAL INTERFACE
6.1INTRODUCTION
The SEM provides two industry standard 2–Wire serial
interfaces for processor–processor and processor–
slave bi–directional communication. The major fea-
tures of these buses include:Only two signal lines are required per bus: a serial
clock line (SCL) and a serial data line (SDA).Each device connected to the bus is software
addressable by a unique address.Masters can operate as Master–transmitter or Mas-
ter–receiver.Multiple master capability via collision detection and
arbitration to prevent data corruption if two or more
masters simultaneously initiate a data transfer.Serial clock synchronization allows devices with dif-
ferent bit rates to communicate via the same serial
bus.Devices can be added to or removed from the bus
without affecting any other circuit on the bus.
Both on–chip 2–Wire ports support four modes of
operation: Master transmitter, Master receiver, Slave
transmitter, Slave receiver. Byte–oriented data trans-
port, clock generation, address recognition, and bus
control arbitration are all performed by the hardware.
Double–buffering is provided on receive, allowing a full
word time to service the port during multiple byte data
transfers.
Figure 6–1 is a block diagram which illustrates the hard-
ware of both 2–Wire serial ports. For simplicity “x” rep-
resents 1 for Port 1 and 2 for Port 2.
2–WIRE SERIAL PORT BLOCK DIAGRAM Figure 6–1
ADDRESS
COMPARE
2WSADRx – ADDRESS
REGISTER
2WCONx – CONTROL
REGISTER
2WFSx – FREQUENCY
SELECT
DIVIDE BY
RELOAD VALUE
R/W
09AH
0DAH
R/W
09DH
0D9H
R/W
09CH
0D3H
DIVIDE BY
8 PRESCALE
tMCLK
2WSTAT1x – STATUS
REGISTER
2WSTAT2x – STATUS
REGISTER
R/W
09EH
0DAH
09FH
0DBH
2WDATx – RECEIVE
DATA BUFFERRD
09BH
0D2H
SHIFT
REGISTERWR
09BH
0D2H
DOUT
DINACK
TIMING &
CONTROL
LOGIC
MSBLSB
ARBITRATION
LOGIC
SERIAL
CLOCK GEN.
SDAx
PIN
SCLx
PIN
INTERNAL
DATA BUS
DS80CH11
011200 34/88
6.2REGISTER DESCRIPTION
The microcontroller interface to either 2–Wire serial port
consists of six Special Function Registers (SFR’s), per
Port, which are documented below. None of these reg-
isters are bit addressable.
6.2.12WFSx – 2–Wire Frequency Select Registers
2WFS1; SFR ADDR.=09CH, 2WFS2; SFR ADDR.=0D3H
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The 2–Wire Frequency Select Registers are 8–bit read/
write registers which are used by the microcontroller to
set the 2–Wire clock data rate. The value programmed
into these registers sets the reload value for an 8–bit
auto–reload timer, which is clocked by the CPU
machine clock (tMCLK) through a divide–by–8 prescaler.
The CPU machine clock period is the oscillator clock
period (tCLK) multiplied times 4, 64, or 1024 as deter-
mined by the programming of the system clock divider
bits (CD1, CD0) in the PMR register. The 2–wire clock
frequency can therefore be calculated using the follow-
ing formula:
f2Wx = fMCLK /((8 * Reload) +2); t2WCL= 1 / f2Wx
whereReload=(2WFSx register value) for 2–255,
and
Reload=(256) for 2WFSx value=0
Reload=(1) is invalid
6.2.22WDATx – 2–Wire Data I/O Registers
2WDAT1; SFR ADDR.=09BH, 2WDAT2; SFR ADDR.=0D2H
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The Data I/O Registers consist of transmit buffers and
the receive buffers. Both registers are located at SFR
address 9BH for Port 1 and D2H for Port 2. A write to
these locations results in a write to the transmit buffer
registers, while a read results in a read from the receive
buffer registers.
During transmit, a write to these locations results in
8–bits of data being transmitted on the 2–Wire bus when
either master or slave transmit mode is established.
When master or slave receive mode is in effect, 8–bits
are shifted in via the shift register and immediately
transferred to the receive buffer. All data is shifted MSB
first.
6.2.32WSADRx – 2–Wire Slave Address Registers
2WSADR1; SFR ADDR.=09AH, 2WSADR2; SFR ADDR.=0D1H
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
SLA6SLA5SLA4SLA3SLA2SLA1SLA0–
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
SLA6–0 – Slave Address bits
SLA6–0 are used to establish the 7–bit address recog-
nized by the 2–Wire port when it is operating in slave
mode. The 7–bit slave address is MSB justified when it
is read or written by the firmware. When read, bit 0 is
always returned as a 0.
DS80CH11
011200 35/88
6.2.42WCONx – 2–Wire Control Registers
2WCON1; SFR ADDR.=09DH, 2WCON2; SFR ADDR.=0D9H
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
2WENxSTAxSTOx2WIFxBMMxANAKx––
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The 2–Wire Control Register bits <7:2> can be read or
written by the microcontroller. Bit <1,0> are reserved for
future use and should be ignored by the firmware. Refer
to the bit description below for specific set/reset condi-
tions.
2WENx – 2–Wire Enable
When 0, the 2–Wire port is disabled. SCLx and SDAx
pins are off (high–Z), no internal processing or bus mon-
itoring is performed, and all internal registers are reset.
If SDAx and SCLx are left connected to the 2–Wire bus
with 2WENx = 0, the serial interface hardware will not
generate or respond to activity on the bus. Also when
2WENx = 0, SDAx and SCLx can be used as open drain
general purpose I/O port pins (P1.5, P1.3, P1.4, and
P1.2, respectively) and are accessible via the port 1
latch register.
When 2WENx = 1, the 2–Wire interface is enabled.
P1.5, P1.4, P1.3 and P1.2 port latches must be set to 1
in order for both serial interfaces, to operate.
STAx – 2–Wire Start
The firmware can generate a start or a repeat start
condition by setting STAx=1 with STOx=0. The hard-
ware will then wait for the bus to be free, and generate a
start condition on the bus in an attempt to gain control of
the bus as a master. If the start condition fails, or if the
port loses arbitration, the hardware will repeat its
attempt until it is successful as long as STAx=1. When
the START condition is successfully asserted, the
TSTAx flag will be set.
If the STAx bit remains set while in the master mode
throughout the time that a byte is being transmitted or
received, then a repeat START condition will be
asserted at the end of the byte transfer. Again, TSTAx
will be set when the repeat start is successfully
asserted.
If STAx is cleared to 0, no further START or repeat
START will be attempted.
STOx – 2–Wire Stop
If STOx=1 when the hardware has control of the bus as
a master, a stop condition is issued on the bus after the
transmit or receive of any byte currently in progress is
completed. When the STOP condition is transmitted on
the bus, the STOx flag will automatically be cleared to 0.
If both STAx and STOx are set in the master mode, the
STOP condition will be generated first. After the STOx
bit is cleared a START will be generated.
When STOx=0, no STOP condition is generated.
2WIFx – 2–Wire Interrupt Flags
2WIFx serves as the main interrupt flag bit for the
2–Wire port. If BMMx = 0, (in 2WCONx register) 2WIFx
is set to 1 whenever operating as a master or as an
addressed slave and one or more of the following inter-
rupt source bits in 2–Wire Status Register (2WSTAT1x)
are set (active): BERx, ARLx, RSTOx, TXIx, RXIx,
TSTAx.
When BMMx=1, the 2WIFx flag will be set when any of
the following source bits are set: BERx, ARLx, RSTOx,
TXIx, RXIx, TSTAx, RSTAx. Note that in this case
RSTAx also generates an interrupt.
Regardless of the state of the BMMx bit, the 2WIFx bit
will be cleared when all of its source bits are cleared.
BMMx – Bus Monitor Mode
When BMMx=0, the 2–Wire port will only generate inter-
rupts if it is operating as a master or being addressed as
a slave.
If bus monitoring is enabled with BMMx = 1, the port can
“listen” to (receive) packets sent from external masters
to external slaves on the 2–Wire bus. In this mode the
DS80CH11
011200 36/88
port will generate an interrupt for every action on the bus
even when it is not operating as a master or being
addressed as a slave. As a result, when a transfer takes
place between an external master and slave, the port
will be notified of a transmitted START condition, will
receive the subsequent address and data bytes on the
bus, and will finally be notified of a transmitted STOP
condition.
ANAKx – Assert Negative AcKnowledge
If ANAKx is set to 1, a negative acknowledge bit will be
returned on the next serial word received. If it is 0, a pos-
itive acknowledge bit will be returned.
6.2.52WSTAT1x – 2–Wire Status Register 1
2WSTAT11; SFR ADDR.=09EH, 2WSTAT12; SFR ADDR.=0DAH
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
BERxARLxRSTOxTXIxRXIxTSTAxRSTAx–
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
BERx – Bus ERror
BERx is a status flag which will be set to 1 in the event
that a stop condition is received with greater or less than
8 bits shifted. BERx is cleared when the 2WSTAT1x
register is read.
ARLx – ARbitration Loss
This bit is set to a 1 when the 2–Wire hardware loses
arbitration to another master on the bus. ARLx is
cleared when the 2WSTAT1x register is read. If arbitra-
tion is lost, the bus will enter the not–addressed slave
state and will receive data beginning with the byte where
arbitration was lost.
RSTOx – Received STOP
RSTOx is set when a valid stop condition is received
when operating as a slave. RSTOx is cleared when the
2WSTAT1x register is read.
TXIx – Transmit Interrupt Flags
During transmit, TXIx is set when a byte has been com-
pletely shifted out and the acknowledge bit received
from the slave. The TXIx flag must be cleared by firm-
ware before any data written to the transmit buffer can
be transmitted, or after setting STAx or STOx bits. If
TXIx is not cleared the 2–Wire bus will be held low until it
is cleared.
RXIx – Receive Interrupt Flags
During receive, RXIx is set when the receive buffer reg-
ister is loaded with a byte of data which has just been
shifted in. The RXIx flag must be cleared by firmware
before the next byte of data can be shifted in.
TSTAx – Transmitted Start
TSTAx will be set to a 1 when a START condition has
been successfully transmitted on the 2–Wire bus. The
TSTAx must be cleared by firmware before the trans-
mission can begin if not the 2–Wire bus will be held low
until it is cleared.
RSTAx – Received Start
RSTAx = 1 when a START condition has been detected
on the bus. RSTAx will be cleared to 0 when the
2WSTAT1x register is read. If BMMx = 0, RSTAx does
not affect the setting of 2WIFx. If BMMx = 1, then RSTAx
will set 2WIFx.
6.2.62WSTAT2x – 2–Wire Status Register 2
2WSTAT21; SFR ADDR.=09FH, 2WSTAT22; SFR ADDR.=0DBH
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
BBxADMxX/RxACKSx––––
Read/Write Access: Read Only.
Initialization: 00H on any type of reset
DS80CH11
011200 37/88
BBx – Bus Busy
This bit is used to signal the microcontroller that the
2–Wire bus is currently in use either by another master
or by the microcontroller itself. It will be set at detection
(or transmission) of a START and will be reset at detec-
tion (or transmission) of STOP.
ADMx – ADdress Match
This bit is set to a 1 when an address has been received
which either matches the value stored in the Address
Register or is the General Call address (00H). The
received address is available in the receive buffer. RXIx
will also be set when an address is received. ADMx will
stay set until a STOP or repeat START is generated.
X/Rx – Xmit / Receive
When X/Rx is set to 1, the 2–Wire port has entered
transmit mode. When X/Rx is cleared to 0, receive
mode operation is signaled.
ACKSx – ACKnowledge Status
ACKSx reflects the state of the acknowledge bit at the
end of a byte transfer on the bus. If a positive acknowl-
edge was detected, ACKSx will be set to 1. If a negative
acknowledge is detected, ACKSx will be cleared to 0.
6.3OPERATIONAL DESCRIPTION
A typical 2–Wire bus configuration is shown in Figure
6–2 and Figure 6–3 illustrates how a data transfer is per-
formed. Two types of data transfers are possible on the
2–Wire bus:Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address with the R/W bit set to 0 (write), fol-
lowed by a number of data bytes. The slave returns
an acknowledge bit after each received byte.Data transfer from a slave transmitter to a master
receiver. The first byte is again the slave address,
this time with the R/W bit set to 1 (read). The slave
returns an acknowledge bit for this first byte. Next,
the slave will transmit the pre–determined number of
data bytes to the master. The master returns an
acknowledge bit after each byte is received for all
but the last byte. At the end of the last byte, the mas-
ter returns a negative acknowledge. This action sig-
nals the slave to stop transmitting.
In both types of transfers, the master generates all of the
serial clock pulses as well as the START and STOP
conditions. A transfer is ended with a STOP condition or
with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the 2–Wire bus will not be released in this case.
Both on–chip 2–Wire ports support four modes of
operation: Master transmitter, Master receiver, Slave
transmitter, and Slave Receiver. Operating the ports in
these four modes is described in detail below. Following
any type of reset, both 2–Wire ports will be configured in
slave receive mode.
TYPICAL 2–WIRE BUS CONFIGURATION Figure 6–2
P1.3 / SDA1P1.2 / SCL1
SEM
DS1307
SERIAL RTC
DS1621
DIGITAL
THERMOMETER
8–BIT uC
w/ 2–Wire I/F
SDA
SCL
VCCRP
P1.5 / SDA2P1.4 / SCL2
DS80CH11
011200 38/88
DATA TRANSFER ON EITHER 2–WIRE BUS Figure 6–3
SDAx
SCLx
MSB
SLAVE ADDRESS
REPEATED FOR
MULTI–BYTE XFERSCLOCK LINE HELD LOW
XMIT: UNTIL SHIFT REG. LOAD
RECEIVE: REC. BUF. FULL3, 6789
ACK23, 89
ACK
R/W
DIR. BIT
ACK
FROM
RECEIVER
NAK
FROM
RECEIVER
ACK
FROM
RECEIVER
CONDITION
STOP
REPEAT
START
STOP OR
REPEAT START
CONDITION
START
CONDITION
6.3.1Master Transmit
In the master transmit mode, the SEM is configured as a
master device and transfers a number of data bytes to a
slave receiver. A timing diagram in Figure 6–4 illus-
trates the interaction between the firmware and hard-
ware with respect to events on the 2–Wire bus.
The master transmit mode can now be entered by set-
ting the STAx bit. The 2–Wire port logic will test the
2–Wire bus and generate a start condition as soon as
the bus is free. As soon as the start condition is trans-
mitted, the TSTAx flag will be set. In addition, the X/Rx
bit will be set to a 1, indicating transmit operation is in
effect.
In response to TSTAx being set, the firmware can now
write to the transmit buffer an initial byte for the message
as follows:6543210
7–bit Slave Address0
MASTER TRANSMIT OPERATION TIMING Figure 6–4
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇ
ÇÇÇ
DATASLAVE ADDR.R/WSA
A/A
DATA
ÉÉÉÉ
ÉÉÉÉ
SLAVE ADDR.
ÇÇÇ
ÇÇÇ
DATAR/WA
A/AÇÇSDAx/SCLx
STAx BIT
X/Rx BIT
XMIT BUF
WRITE
TSTAx BIT
TXIx BIT
ACKSx BIT
STOx BIT
ACTION TAKEN BY FIRMWAREMASTER TO SLAVE XFER
ALTERNATIVE CONDITIONSLAVE TO MASTER XFER
A = ACKNOWLEDGE (SDAx LOW)
A = NEGATIVE ACKNOWLEDGE (SDAx HIGH)
S = START CONDITION
Sr = REPEAT START CONDITION
P = STOP CONDITION
DS80CH11
011200 39/88
The desired slave address is placed in the most signifi-
cant 7–bits and a “0” in the least significant bit (direction
bit position) indicating a write operation. Transmission
of this byte will begin immediately upon writing the byte.
After writing the byte, the firmware must clear the TSTAx
and STAx bits. The firmware can now exit the interrupt
service routine or otherwise wait until the initial byte is
transmitted.
When the slave address and direction bit have been
sent and a positive acknowledge bit received back from
the slave, the TXIx bit will be set, indicating the transmis-
sion is complete. At this point the firmware can load the
first data byte into the transmit buffer and then clear the
TXIx bit. Because transmit mode is now in effect, clear-
ing TXIx causes the hardware to load the contents of the
buffer into the shift register. Therefore loading the buffer
before clearing TXIx will insure that the hardware will not
load the previous byte into the shift register and thereby
re–transmit it. Subsequent data bytes can be success-
fully transmitted each time TXIx is set by repeating the
above procedure. In the event that a negative acknowl-
edge bit is received back from the slave after sending
any bytes, the transmission can be aborted by issuing a
repeat START or STOP condition as described below.
As shown in the diagram, a repeat start condition can be
sent following the transmission of a data byte. In this
case the firmware should first set STAx to a 1 after
detecting that the TXIx flag is set. Since the port logic
has control of the bus, a repeat START condition will be
issued immediately, resulting in TSTAx being set to 1.
The firmware must then reset TSTAx, write the next
slave address and direction bit (0 = master transmit) to
the transmit buffer, and clear TXIx to 0. This sequence
will insure that the repeat start is sent before the data
containing the slave address is transmitted. Finally, the
STAx bit should be cleared to 0 so that another repeat
START will not be sent following the slave address byte.
Subsequent data bytes can then be transmitted as
described above.
When TXIx is set after the last byte of data has been
transmitted, a STOP condition can be issued by setting
the STOx bit to a 1. The TXIx bit must be cleared at this
point by firmware; this action will not cause any addi-
tional data to be sent since the port will be in receive
mode as a result of setting STOx. After the STOP condi-
tion is sent, the STOx bit will be automatically cleared
and X/Rx will be cleared to 0.
In the Master transmit mode, the arbitration logic checks
that every transmitted logic 1 actually appears as a logic
1 on the 2–Wire bus. If another device on the bus over-
rules a logic 1 and pulls the SDAx line low, arbitration is
lost, and the port logic immediately changes from Mas-
ter transmit mode to Slave Receive mode. The port
logic will continue to output clock pulses on SCLx until
transmission of the current serial byte is complete. At
the completion of the byte, the ARLx bit will be set to a 1.
The resulting transmitted serial word from the master
which won the arbitration will be available in the receive
buffer. If arbitration was lost during the transmission of
the slave address and the resulting address matches
the port’s programmed slave address in 2WSADRx,
then the ADMx bit will also be set to 1.
6.3.2Master Receive
Figure 6–5 illustrates Master Receive operation. In
Master Receive mode, the SEM is configured as a mas-
ter and one or more data bytes are received from a slave
device.
The transfer is initiated as in the Master Transmit mode,
beginning with either a start condition or a repeat start
condition, followed by the transmission of the slave
address. However, in this case the direction bit should
be set to a 1 to signal Master Receive operation.
When the acknowledge bit for the slave address is
sampled, the TXIx bit will be set to a 1 and ACKSx bit will
reflect the state of the bit returned from the slave. Since
the direction bit was set to 1, the X/Rx bit will be cleared
to 0 indicating receive operation is now in effect. The
TXIx bit must be cleared to 0 by firmware to remove the
interrupt condition. No further bytes will be transmitted
in the packet since the port logic is in receive mode.
If it is desired to return a positive acknowledge bit upon
the receipt of subsequent data byte(s), the ANAKx bit
should be cleared to 0. Upon the receipt of the data
byte, the RXIx bit will be set at the time the acknowledge
bit is transmitted. The firmware should read the incom-
ing byte from the receive buffer register followed by a
clear of RXIx to 0. Subsequent incoming data bytes are
handled in the same manner.
After each byte is received and loaded into the receive
buffer and the RXIx flag cleared, the next byte will begin
to be shifted in immediately.
DS80CH11
011200 40/88
MASTER RECEIVE OPERATION TIMING Figure 6–5
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇ
ÇÇÇ
ÇÇÇ
DATASLAVE ADDR.R/WA
DATASDAx/SCLx
ÇÇÇ
ÇÇÇ
ÇÇÇ
DATA
(Sr)
TSTAx BIT
DATA BUF:
WRITE
READ
X/Rx BIT
TXIx BIT
RXIx BIT
ACKSx BIT
ANAKx BIT
STOx BIT
STAx BIT
In response to RXIx being set on the next to the last data
byte, the ANAKx bit can be set so that a negative
acknowledge bit is returned to the slave when the last
data byte is received. This action signals the slave to
stop transmitting bytes and return to receive mode. If
there is only one byte to be received from the slave
device, the ANAKx bit can be set at the time the slave
address is transmitted so that the negative acknowl-
edge signal will be transmitted after the reception of the
single byte.
When the last data byte is received and RXIx cleared,
the STOP condition can be issued by setting the STOx
bit to a 1. ANAKx can be returned to a 0 at this time to
return a positive acknowledge on future received bytes
(e.g., received slave address). After the STOP condi-
tion is sent the STOx bit will be automatically cleared
and X/Rx will remain at 0, indicating the port hardware is
still in receive mode.
Arbitration with another master may be lost during the
transmission of the slave address as described above in
the Master Transmit mode. Once receive operation is in
progress in the Master Receive mode, then arbitration
loss can only occur while a negative acknowledge is
being returned on the bus. In this case arbitration is lost
when another master on the bus pulls this signal low.
Since this occurs at the end of a serial byte, no further
clock pulses are generated. The ARLx flag will be set to
signal this event.
6.3.3Slave Receive
Figure 6–6 illustrates the timing for Slave Receive
operation. In this mode another master transfers one or
more bytes to the SEM which is addressed as a slave
device.
When the 2–Wire ports are initialized following a reset,
the SEM’s 7–bit slave addresses are established by
DS80CH11
011200 41/88
programming the 2WSADRx register with the address
value left–justified. The ANAKx bit should be cleared to
0 to allow a positive acknowledge bit to be issued when
the SEM’s slave address is received.
SLAVE RECEIVE OPERATION TIMING Figure 6–6
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
SLAVE ADDR.R/WASDAx/SCLx
X/Rx BIT
RXIx BIT
ACKSx BIT
ANAKx BIT
ÇÇÇ
ÇÇÇ
ÇÇÇ
DATA
DATA
ÇÇÇ
ÇÇÇ
ÇÇÇ
DATA
A/A
ADMx BIT
RCV BUF.
READ
RSTOx BIT
The transfer is initiated by the external master beginning
with either a START or Repeat START condition, fol-
lowed by the transmission of the SEM’s slave address
with the direction bit cleared to 0. This byte will be
shifted in and loaded into the receive buffer register at
the time the acknowledge bit is returned to the master,
resulting in RXIx being set to 1. In addition, an address
match condition will occur as indicated by the ADMx flag
set to 1. Upon detecting these flags, the firmware
should respond by reading the receive buffer in order to
determine if the programmed slave address or the gen-
eral call address was received. Following the read of
the buffer, the RXIx flag must be cleared. Also at this
time the firmware should insure that the 2WIFx bit is
cleared to 0, so that the interrupt flag will be set in
response to subsequent received data byte(s) and
STOP condition.
Upon the receipt of the first data byte, the RXIx bit will be
set at the time the acknowledge bit is transmitted. The
firmware should read the incoming byte from the receive
buffer register followed by a clear of RXIx to 0. Subse-
quent incoming data bytes are handled in the same
manner. If desired, the ANAKx bit can be set to cause a
negative acknowledge to be issued upon receipt of the
next byte.
When the last byte of data has been sent, the bus mas-
ter will issue a STOP condition, which will result in the
RSTOx flag set to a 1. At this time, the port hardware
returns to the not–addressed slave mode.
6.3.4Slave Transmit
Figure 6–7 illustrates the timing for Slave Transmit
mode operation. In this mode the SEM, addressed as a
slave, transfers one or more bytes to the bus master.
The transfer is initiated by the external master beginning
with either a START or Repeat START condition, fol-
DS80CH11
011200 42/88
lowed by the transmission of the SEM’s slave address
with the direction bit set to 1. This byte will be shifted in
and loaded into the receive buffer register at the time the
acknowledge bit is returned to the master, resulting in
RXIx being set to 1. In addition, an address match
condition will occur as indicated by the ADMx flag
set to 1.
SLAVE TRANSMIT OPERATION TIMING Figure 6–7
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇ
ÇÇÇ
DATASLAVE ADDR.R/WA
DATASDAx/SCLx
ÇÇÇ
ÇÇÇ
DATA
AÇÇ
(Sr)
ADMx BIT
DATA BUF:
WRITE
READ
X/Rx BIT
RXIx BIT
TXIx BIT
ACKSx BIT
RSTOx BIT
Upon detecting these flags, the firmware should
respond by reading the receive buffer in order to deter-
mine if the programmed slave address or the general
call address was received. Following the read of the
buffer, the RXIx flag must be cleared. Also at this time
the firmware should insure that the 2WIFx bit is cleared
to 0, so that the interrupt flag will be set in response to
subsequent received data byte(s) and STOP condition.
If the programmed slave address was received, the
firmware can now send the first data byte by a write to
the transmit buffer. After the first data byte is transmitted
and the acknowledge bit received, the TXIx flag will be
set to 1. If the acknowledge bit ACKSx is returned as a
1, the next byte can be loaded into the transmit buffer
and the TXIx bit cleared. Successive bytes can be han-
dled in the same manner. Whenever any data is trans-
mitted from the 2–Wire port, the byte actually trans-
ferred on the bus will be shifted back in and loaded into
the receive buffer.
If the acknowledge bit ACKSx is returned as a 0 on a
transmitted byte, then the master is signaling this as the
last data byte in the packet. In this event, the X/Rx bit will
be automatically cleared to 0 and the firmware should
not write any more data bytes to the transmit buffer. The
TXIx bit must be cleared at this point by firmware; this
action will not cause any additional data to be sent since
the port is now in receive mode.
When the last byte of data has been sent, the bus mas-
ter will issue a STOP condition, which will result in the
RSTOx bit set to a 1. At this time, the port hardware
returns to the not–addressed slave mode.
DS80CH11
011200 43/88
6.3.5Bus Monitor Mode Operation
The bus monitor mode is provided to allow the SEM to
“listen” as a third party to conversations between exter-
nal master and slave devices. This mode can be useful
for diagnostic purposes, or to help the system recover
from a detected error condition.
When the BMMx bit is set to 1, bus monitoring is
enabled. In this mode the port will generate an interrupt
for every action on the bus even when it is not operating
as a master or being addressed as a slave. As a result,
when a transfer takes place between an external master
and slave, the port will be notified of a transmitted
START condition, will receive the subsequent address
and data bytes on the bus, and will finally be notified of a
transmitted STOP condition.
If the SEM is receiving a transfer between an external
master and an external slave device, the timing is nearly
identical to that for Slave Receive operation as shown in
Figure 6–6. The exceptions to this timing are summa-
rized as follows: 1) An additional interrupt will be gener-
ated when a Receive START condition is detected as
indicated by RSTAx = 1. This will inform the firmware of
the start of a message and allow it to identify the next
byte as an address. 2) A positive acknowledge pulse
will never be generated. 3) SCLx will never be held low
to prevent data in the receive buffer from being overwrit-
ten. Other than these differences bytes are received
and all other status is flagged as described for Slave
Receiver operation.
When BMMx = 1 and the SEM is operating as a master
or is being addressed as a slave, the Master Transmit,
Master Receive, Slave Transmit, and Slave Receive
modes will all operate exactly as documented above
with the exception that RSTAx becomes an additional
interrupt flag that is set whenever a START condition is
detected on the bus.
When BMMx = 0, bus monitoring is disabled and inter-
rupt flags are only generated when the port is operating
as a master or being addressed as a slave device.
Transfers between external devices are ignored.
DS80CH11
011200 44/88
7.0A/D CONVERTER
7.1OVERVIEW
A self–contained A/D converter is provided on the SEM.
Its major features are summarized below:10–bit resolutionTrue 9–bit accuracy: total error no greater than + 2
LSB’sMonotonic with no missing codeseight multiplexed inputsShared analog/digital pins with 60 dB isolationDigital window comparator / alarmLow power consumption
The A/D subsystem consists of a 10–bit successive
approximation analog to digital converter, an 8 input
analog multiplexor, a programmable reference block, a
digital window comparator, and a control block as
depicted in Figure 7–1.
The multiplexor selects 1 of 8 analog inputs for conver-
sion. A conversion is initiated either by a software or
hardware generated start of conversion signal. An
optional mode enables continuous conversions on a
selected channel. At the completion of a conversion the
A/D generates an end of conversion signal indicating
that the conversion is complete and the results may be
read. An end of conversion can also be used to gener-
ate an interrupt.
After the conversion is complete, the 10–bit result is
available in two registers. In order to accommodate a
variety of applications, the A/D result can be pro-
grammed to be presented either as eight msbs and
eight lsbs in separate registers, or as a right justified
10–bit result with the most significant two bits of the
result right–justified in the most significant byte. An A/D
conversion can be performed in a minimum of 16 msec.
An interrupt can be programmed to occur at the end of a
conversion.
A digital window comparator is available to allow auto-
matic monitoring of external signals without burdening
the software. The window comparator allows software
to select an upper and lower limit for comparison. In
addition, the hardware can be programmed to look
inside or outside of the window. By adjusting the win-
dow location, the hardware can automatically look for
results that are above a number, below a number, inside
of a range, or outside of a range. When the window
comparator qualifier function is used, an end–of–con-
version interrupt will only be generated when selected
criteria for the conversion result has been met.
7.2ANALOG POWER / SLEEP MODE
The A/D block provides separate power and ground
pins to provide power to the analog circuits. This allows
the A/D to operate from a clean supply if available. Ana-
log power is supplied through AVCC and AGND. While
these pins do supply power, they are not the source of
the A/D reference. The converter will draw a maximum
of 1 mA during full operation.
A minimum time of tAD required for the analog circuitry to
stabilize. The ADON bit is cleared to 0 following a reset
– leaving the A/D converter powered down.

Partno	Mfg	Dc	Qty	Available	Descript
DS80CH11	DALLAS	N/a	760	avai	System Energy Manager