DS50PCI402SQ/NOPB ,2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis 54-WQFN -10 to 85FEATURES DESCRIPTIONThe DS50PCI402 is a low power, 4 lane bidirectional2• Input and Output signal c ..
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DS50PCI402SQ/NOPB
2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis
DS50PCI402
www.ti.com SNLS320H –APRIL 2010–REVISED MARCH 2013
DS50PCI402 2.5 Gbps/ 5.0 Gbps4 Lane PCI Express Repeater with
Equalization and De-Emphasis
Checkfor Samples: DS50PCI402
1FEATURES DESCRIPTIONThe DS50PCI402isa low power,4 lane bidirectional
Input and Output signal conditioning buffer/equalizer designed specifically for PCI Express
increases PCIe reachin backplanes and Gen1 and Gen2 applications. The device performs
cables both receive equalization and transmit de-emphasis,
• 0.09UIof residual deterministic jitterat 5Gbps allowing maximum flexibilityof physical placement
after 42”of FR4 (with Input EQ) withina system. The receiveris capableof opening input eye thatis completely closed dueto inter-
• 0.11UIof residual deterministic jitterat 5Gbps symbol interference (ISI) inducedby the interconnect
after 7mof PCIe Cable (with Input EQ) medium.
• 0.09UIof residual deterministic jitterat 5GbpsThe transmitter de-emphasis level can be set by the
with 28”of FR4 (with Output DE)user depending on the distance from the
• 0.13UIof residual deterministic jitterat 5Gbps DS50PCI402 to the PCI Express endpoint. The
with 7mof PCIe Cable (with Output DE) DS50PCI402 contains PCI Express specific functions
• Adjustable Transmit VOD 800to 1200mVp-p such as Transmit Idle, RX Detection, and Beacon
signal pass through.
• Automatic and manual Receiver Detection and
input termination control circuitry The device provides automatic receive detection
Automatic power management onan circuitry which controls the input termination
impedance. By automatically reflecting the current
individual lane basis via SMBusload impedance seen on the outputs backto the
• Adjustable electrical idle detect threshold. corresponding inputs the DS50PCI402 becomes
• Data rate optimized 3-stage equalizationto 27 completely transparentto both the PCIe root complex
dB gain and endpoint. An internal rate detection circuitis
includedto detectif an incoming data streamisat
• Data rate optimized 6-level0to12 dB transmitGen2 data rates, and adjusts the de-emphasis on it's
de-emphasis output accordingly. The signal conditioning provided
• Flow-thru pinoutin 10mmx5.5mm 54-pin by the device allows systemsto upgrade from Gen1
leadless WQFN package data ratesto Gen2 without reducing their physical
Single supply operationat 2.5V reach. Thisis true for FR4 applications such as
backplanes,as wellas cable interconnect.
• >6kV HBM ESD rating temperature range
