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DS26524DALLASN/a295avaiQuad T1/E1/J1 Transceiver


DS26524 ,Quad T1/E1/J1 TransceiverApplications Routers Crystal-Less Jitter Attenuator can be Selected Channel Service Units (CSUs) ..
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DS26524
Quad T1/E1/J1 Transceiver
GENERAL DESCRIPTION
The DS26524 is a single-chip 4-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
APPLICATIONS

Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
TYPICAL OPERATING CIRCUIT
DS26524
T1/J1/E1
Transceiver

T1/E1/J1
NETWORK
BACKPLANE
TDM
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE

DS26524G 0°C to +70°C 256 TE-CSBGA
DS26524G+ 0°C to +70°C 256 TE-CSBGA
DS26524GN -40°C to +85°C 256 TE-CSBGA
DS26524GN+ -40°C to +85°C 256 TE-CSBGA
+ Denotes lead-free/RoHS compliant device.
FEATURES
Four Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion T1 Framing Formats of D4, SLC-96, and ESF J1 Support E1 G.704 and CRC-4 Multiframe T1-to-E1 Conversion
Features Continued in Section 2.

DS26524
Quad T1/E1/J1 Transceiver

DS26524 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9

1.1 MAJOR OPERATING MODES.............................................................................................................9
2. FEATURE HIGHLIGHTS..................................................................................................10

2.1 GENERAL......................................................................................................................................10
2.2 LINE INTERFACE............................................................................................................................10
2.3 CLOCK SYNTHESIZER....................................................................................................................10
2.4 JITTER ATTENUATOR.....................................................................................................................10
2.5 FRAMER/FORMATTER....................................................................................................................10
2.6 SYSTEM INTERFACE......................................................................................................................11
2.7 HDLC CONTROLLERS...................................................................................................................12
2.8 TEST AND DIAGNOSTICS................................................................................................................12
2.9 CONTROL PORT............................................................................................................................12
3. APPLICATIONS...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE...................................................................................14
5. ACRONYMS AND GLOSSARY.......................................................................................16
6. BLOCK DIAGRAMS.........................................................................................................17
7. PIN DESCRIPTIONS........................................................................................................19

7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................19
8. FUNCTIONAL DESCRIPTION.........................................................................................26

8.1 PROCESSOR INTERFACE................................................................................................................26
8.2 CLOCK STRUCTURE.......................................................................................................................26
8.2.1 Backplane Clock Generation...............................................................................................................26
8.3 RESETS AND POWER-DOWN MODES..............................................................................................28
8.4 INITIALIZATION AND CONFIGURATION..............................................................................................29
8.4.1 Example Device Initialization Sequence..............................................................................................29
8.5 GLOBAL RESOURCES....................................................................................................................29
8.6 PER-PORT RESOURCES................................................................................................................29
8.7 DEVICE INTERRUPTS.....................................................................................................................29
8.8 SYSTEM BACKPLANE INTERFACE...................................................................................................31
8.8.1 Elastic Stores.......................................................................................................................................31
8.8.2 IBO Multiplexer.....................................................................................................................................34
8.8.3 H.100 (CT Bus) Compatibility..............................................................................................................40
8.8.4 Receive and Transmit Channel Blocking Registers.............................................................................41
8.8.5 Transmit Fractional Support (Gapped Clock Mode)............................................................................41
8.8.6 Receive Fractional Support (Gapped Clock Mode).............................................................................41
8.9 FRAMERS......................................................................................................................................42
8.9.1 T1 Framing...........................................................................................................................................42
8.9.2 E1 Framing...........................................................................................................................................45
8.9.3 T1 Transmit Synchronizer....................................................................................................................47
8.9.4 Signaling..............................................................................................................................................48
8.9.5 T1 Data Link.........................................................................................................................................52
8.9.6 E1 Data Link.........................................................................................................................................54
8.9.7 Maintenance and Alarms.....................................................................................................................55
8.9.8 E1 Automatic Alarm Generation..........................................................................................................58
8.9.9 Error-Count Registers..........................................................................................................................59
DS26524 Quad T1/E1/J1 Transceiver
8.9.12 Receive Per-Channel Idle Code Insertion............................................................................................62
8.9.13 Per-Channel Loopback........................................................................................................................62
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)...................................................................62
8.9.15 T1 Programmable In-Band Loop Code Generator...............................................................................63
8.9.16 T1 Programmable In-Band Loop Code Detection................................................................................64
8.9.17 Framer Payload Loopbacks.................................................................................................................65
8.10 HDLC CONTROLLERS................................................................................................................66
8.10.1 Receive HDLC Controller.....................................................................................................................66
8.10.2 Transmit HDLC Controller....................................................................................................................69
8.11 LINE INTERFACE UNITS (LIUS)....................................................................................................71
8.11.1 LIU Operation.......................................................................................................................................74
8.11.2 Transmitter...........................................................................................................................................75
8.11.3 Receiver...............................................................................................................................................78
8.11.4 Jitter Attenuator....................................................................................................................................81
8.11.5 LIU Loopbacks.....................................................................................................................................82
8.12 BIT-ERROR-RATE TEST (BERT) FUNCTION................................................................................84
8.12.1 BERT Repetitive Pattern Set...............................................................................................................85
8.12.2 BERT Error Counter.............................................................................................................................85
9. DEVICE REGISTERS.......................................................................................................86

9.1 REGISTER LISTINGS......................................................................................................................86
9.1.1 Global Register List..............................................................................................................................88
9.1.2 Framer Register List.............................................................................................................................89
9.1.3 LIU and BERT Register List.................................................................................................................96
9.2 REGISTER BIT MAPS......................................................................................................................97
9.2.1 Global Register Bit Map.......................................................................................................................97
9.2.2 Framer Register Bit Map......................................................................................................................98
9.2.3 LIU Register Bit Map..........................................................................................................................106
9.2.4 BERT Register Bit Map......................................................................................................................106
9.3 GLOBAL REGISTER DEFINITIONS..................................................................................................107
9.4 FRAMER REGISTER DEFINITIONS.................................................................................................122
9.4.1 Receive Register Definitions..............................................................................................................122
9.4.2 Transmit Register Definitions.............................................................................................................181
9.5 LIU REGISTER DEFINITIONS.........................................................................................................216
9.6 BERT REGISTER DEFINITIONS.....................................................................................................225
10. FUNCTIONAL TIMING...................................................................................................233

10.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................233
10.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................238
10.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................243
10.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................245
11. OPERATING PARAMETERS.........................................................................................248

11.1 THERMAL CHARACTERISTICS....................................................................................................249
11.2 LINE INTERFACE CHARACTERISTICS..........................................................................................249
12. AC TIMING CHARACTERISTICS..................................................................................250

12.1 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................250
12.2 JTAG INTERFACE TIMING.........................................................................................................259
12.3 SYSTEM CLOCK AC CHARACTERISTICS....................................................................................260
13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT................................................261

13.1 TAP CONTROLLER STATE MACHINE.........................................................................................262
13.1.1 Test-Logic-Reset................................................................................................................................262
13.1.2 Run-Test-Idle.....................................................................................................................................262
DS26524 Quad T1/E1/J1 Transceiver
13.1.5 Shift-DR..............................................................................................................................................262
13.1.6 Exit1-DR.............................................................................................................................................262
13.1.7 Pause-DR...........................................................................................................................................262
13.1.8 Exit2-DR.............................................................................................................................................262
13.1.9 Update-DR.........................................................................................................................................262
13.1.10 Select-IR-Scan...............................................................................................................................262
13.1.11 Capture-IR......................................................................................................................................263
13.1.12 Shift-IR............................................................................................................................................263
13.1.13 Exit1-IR...........................................................................................................................................263
13.1.14 Pause-IR.........................................................................................................................................263
13.1.15 Exit2-IR...........................................................................................................................................263
13.1.16 Update-IR.......................................................................................................................................263
13.2 INSTRUCTION REGISTER...........................................................................................................265
13.2.1 SAMPLE:PRELOAD..........................................................................................................................265
13.2.2 BYPASS.............................................................................................................................................265
13.2.3 EXTEST.............................................................................................................................................265
13.2.4 CLAMP...............................................................................................................................................265
13.2.5 HIGHZ................................................................................................................................................265
13.2.6 IDCODE.............................................................................................................................................265
13.3 JTAG ID CODES......................................................................................................................266
13.4 TEST REGISTERS.....................................................................................................................266
13.4.1 Boundary Scan Register....................................................................................................................266
13.4.2 Bypass Register.................................................................................................................................266
13.4.3 Identification Register.........................................................................................................................266
14. PIN CONFIGURATION...................................................................................................271
15. PACKAGE INFORMATION............................................................................................272

15.1 256-BALL TE-CSBGA (56-G6028-001)...................................................................................272
16. DOCUMENT REVISION HISTORY................................................................................273
DS26524 Quad T1/E1/J1 Transceiver
LIST OF FIGURES

Figure 6-1. Block Diagram.........................................................................................................................................17
Figure 6-2. Detailed Block Diagram...........................................................................................................................18
Figure 8-1. Backplane Clock Generation...................................................................................................................27
Figure 8-2. Device Interrupt Information Flow Diagram.............................................................................................30
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz......................................................................................35
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz......................................................................................36
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz....................................................................................37
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode...................................................................................................40
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode.......................................................................41
Figure 8-8. CRC-4 Recalculate Method....................................................................................................................62
Figure 8-9. Receive HDLC Example..........................................................................................................................68
Figure 8-10. HDLC Message Transmit Example.......................................................................................................70
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal Protection.............................72
Figure 8-12. T1/J1 Transmit Pulse Templates..........................................................................................................76
Figure 8-13. E1 Transmit Pulse Templates...............................................................................................................77
Figure 8-14. Typical Monitor Application...................................................................................................................79
Figure 8-15. Jitter Attenuation...................................................................................................................................81
Figure 8-16. Analog Loopback...................................................................................................................................82
Figure 8-17. Local Loopback.....................................................................................................................................82
Figure 8-18. Remote Loopback.................................................................................................................................83
Figure 8-19. Dual Loopback......................................................................................................................................83
Figure 9-1. Register Memory Map for the DS26524..................................................................................................87
Figure 10-1. T1 Receive-Side D4 Timing................................................................................................................233
Figure 10-2. T1 Receive-Side ESF Timing..............................................................................................................233
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)...............................................................234
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................234
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................235
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode..................................................................236
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode..............................................................237
Figure 10-8. T1 Transmit-Side D4 Timing...............................................................................................................238
Figure 10-9. T1 Transmit-Side ESF Timing.............................................................................................................238
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................239
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................239
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................240
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode...............................................................241
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode....................................................................242
Figure 10-15. E1 Receive-Side Timing....................................................................................................................243
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................243
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................244
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................244
Figure 10-19. E1 Transmit-Side Timing...................................................................................................................245
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................245
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................246
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................246
Figure 10-23. E1 G.802 Timing...............................................................................................................................247
Figure 12-1. Intel Bus Read Timing (BTS = 0)........................................................................................................251
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