DS26521L+ ,Single T1/E1/J1 Transceiverapplications. Each channel is independently Internal Software-Selectable Transmit- and configurab ..
DS26521LN ,Single T1/E1/J1 TransceiverFEATURES Complete T1, E1, or J1 Long-Haul/Short-Haul The DS26521 is a single-channel framer and l ..
DS26521LN+ ,Single T1/E1/J1 TransceiverTABLE OF CONTENTS 1. DETAILED DESCRIPTION.....9 1.1 MAJOR OPERATING MODES.9 2. FEATURE HIGHLIGHTS . ..
DS26522DK ,Dual T1/E1/J1 Transceiver Demo KitFEATURES The DS26522DK is an easy-to-use demo kit for the Demonstrates Key Functions of DS26522 D ..
DS26522G+ ,Dual T1/E1/J1 TransceiverAPPLICATIONS Crystal-Less Jitter Attenuator can be Selected for Transmit or Receive Path; Jitter ..
DS26524 ,Quad T1/E1/J1 TransceiverApplications Routers Crystal-Less Jitter Attenuator can be Selected Channel Service Units (CSUs) ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26521-DS26521L+-DS26521LN-DS26521LN+
Single T1/E1/J1 Transceiver
GENERAL DESCRIPTION The DS26521 is a single-channel framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
APPLICATIONS Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26521
T1/J1/E1
TransceiverT1/E1/J1
NETWORK
BACKPLANE
TDM
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS26521LN -40°C to +85°C 64 LQFP
DS26521LN+ -40°C to +85°C 64 LQFP
+ Denotes lead-free/RoHS compliant device.
FEATURES �
Complete T1, E1, or J1 Long-Haul/Short-Haul
Transceiver (LIU plus Framer) �
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications �
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411 �
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode �
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments �
Transmit Open- and Short-Circuit Detection �
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231 �
Transmit Synchronizer �
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port �
Alarm Detection and Insertion �
T1 Framing Formats of D4, SLC-96, and ESF �
J1 Support �
E1 G.704 and CRC-4 Multiframe �
Controlled by 8-Bit Parallel Port Interface or
Serial Peripheral Interface (SPI)
Features Continued in Section 2.
DS26521
Single T1/E1/J1 Transceiver
DS26521 Single T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION...............................................................................................9 1.1 MAJOR OPERATING MODES.............................................................................................................9
2. FEATURE HIGHLIGHTS................................................................................................10 2.1 GENERAL......................................................................................................................................10
2.2 LINE INTERFACE............................................................................................................................10
2.3 CLOCK SYNTHESIZER....................................................................................................................10
2.4 JITTER ATTENUATOR.....................................................................................................................10
2.5 FRAMER/FORMATTER....................................................................................................................10
2.6 SYSTEM INTERFACE......................................................................................................................11
2.7 HDLC CONTROLLERS...................................................................................................................12
2.8 TEST AND DIAGNOSTICS................................................................................................................12
2.9 MICROCONTROLLER PARALLEL PORT.............................................................................................12
2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES............................................................12
3. APPLICATIONS..............................................................................................................13
4. SPECIFICATIONS COMPLIANCE.................................................................................14
5. ACRONYMS AND GLOSSARY......................................................................................16
6. BLOCK DIAGRAMS.......................................................................................................17
7. PIN DESCRIPTIONS......................................................................................................19 7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................19
8. FUNCTIONAL DESCRIPTION........................................................................................25 8.1 MICROPROCESSOR INTERFACE......................................................................................................25
8.1.1 Parallel Port Mode................................................................................................................................25
8.1.2 SPI Serial Port Mode............................................................................................................................25
8.1.3 SPI Functional Timing Diagrams.........................................................................................................25
8.2 CLOCK STRUCTURE.......................................................................................................................28
8.2.1 Backplane Clock Generation...............................................................................................................28
8.3 RESETS AND POWER-DOWN MODES..............................................................................................29
8.4 INITIALIZATION AND CONFIGURATION..............................................................................................30
8.4.1 Example Device Initialization Sequence..............................................................................................30
8.5 GLOBAL RESOURCES....................................................................................................................30
8.6 PORT RESOURCES........................................................................................................................30
8.7 DEVICE INTERRUPTS.....................................................................................................................30
8.8 SYSTEM BACKPLANE INTERFACE...................................................................................................32
8.8.1 Elastic Stores.......................................................................................................................................32
8.8.2 IBO Multiplexer.....................................................................................................................................35
8.8.3 H.100 (CT Bus) Compatibility..............................................................................................................36
8.8.4 Receive and Transmit Channel Blocking Registers.............................................................................37
8.8.5 Transmit Fractional Support (Gapped Clock Mode)............................................................................37
8.8.6 Receive Fractional Support (Gapped Clock Mode).............................................................................37
8.9 FRAMERS......................................................................................................................................38
8.9.1 T1 Framing...........................................................................................................................................38
8.9.2 E1 Framing...........................................................................................................................................41
8.9.3 T1 Transmit Synchronizer....................................................................................................................43
8.9.4 Signaling..............................................................................................................................................44
8.9.5 T1 Data Link.........................................................................................................................................48
DS26521 Single T1/E1/J1 Transceiver
8.9.8 E1 Automatic Alarm Generation..........................................................................................................54
8.9.9 Error-Count Registers..........................................................................................................................55
8.9.10 DS0 Monitoring Function......................................................................................................................57
8.9.11 Transmit Per-Channel Idle Code Insertion...........................................................................................58
8.9.12 Receive Per-Channel Idle Code Insertion............................................................................................58
8.9.13 Per-Channel Loopback........................................................................................................................58
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)...................................................................58
8.9.15 T1 Programmable In-Band Loop Code Generator...............................................................................59
8.9.16 T1 Programmable In-Band Loop Code Detection................................................................................60
8.9.17 Framer Payload Loopbacks.................................................................................................................61
8.10 HDLC CONTROLLERS................................................................................................................62
8.10.1 Receive HDLC Controller.....................................................................................................................62
8.10.2 Transmit HDLC Controller....................................................................................................................65
8.11 LINE INTERFACE UNITS (LIUS)....................................................................................................67
8.11.1 LIU Operation.......................................................................................................................................69
8.11.2 Transmitter...........................................................................................................................................70
8.11.3 Receiver...............................................................................................................................................73
8.11.4 Jitter Attenuator....................................................................................................................................76
8.11.5 LIU Loopbacks.....................................................................................................................................77
8.12 BIT-ERROR-RATE TEST (BERT) FUNCTION................................................................................79
8.12.1 BERT Repetitive Pattern Set...............................................................................................................80
8.12.2 BERT Error Counter.............................................................................................................................80
9. DEVICE REGISTERS.....................................................................................................81 9.1 REGISTER LISTINGS......................................................................................................................81
9.1.1 Global Register List..............................................................................................................................82
9.1.2 Framer Register List.............................................................................................................................83
9.1.3 LIU and BERT Register List.................................................................................................................90
9.2 REGISTER BIT MAPS......................................................................................................................91
9.2.1 Global Register Bit Map.......................................................................................................................91
9.2.2 Framer Register Bit Map......................................................................................................................92
9.2.3 LIU Register Bit Map..........................................................................................................................100
9.2.4 BERT Register Bit Map......................................................................................................................100
9.3 GLOBAL REGISTER DEFINITIONS..................................................................................................101
9.4 FRAMER REGISTER DEFINITIONS.................................................................................................109
9.4.1 Receive Register Definitions..............................................................................................................109
9.4.2 Transmit Register Definitions.............................................................................................................168
9.5 LIU REGISTER DEFINITIONS.........................................................................................................203
9.6 BERT REGISTER DEFINITIONS.....................................................................................................212
10. FUNCTIONAL TIMING.................................................................................................220 10.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................220
10.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................225
10.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................230
10.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................232
11. OPERATING PARAMETERS.......................................................................................235 11.1 THERMAL CHARACTERISTICS....................................................................................................236
11.2 LINE INTERFACE CHARACTERISTICS..........................................................................................236
12. AC TIMING CHARACTERISTICS................................................................................237 12.1 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................237
12.1.1 Parallel Port Mode..............................................................................................................................237
12.1.2 SPI Bus Mode....................................................................................................................................240
12.2 JTAG INTERFACE TIMING.........................................................................................................248
DS26521 Single T1/E1/J1 Transceiver
13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT..............................................250 13.1 TAP CONTROLLER STATE MACHINE.........................................................................................251
13.1.1 Test-Logic-Reset................................................................................................................................251
13.1.2 Run-Test-Idle.....................................................................................................................................251
13.1.3 Select-DR-Scan.................................................................................................................................251
13.1.4 Capture-DR........................................................................................................................................251
13.1.5 Shift-DR..............................................................................................................................................251
13.1.6 Exit1-DR.............................................................................................................................................251
13.1.7 Pause-DR...........................................................................................................................................251
13.1.8 Exit2-DR.............................................................................................................................................251
13.1.9 Update-DR.........................................................................................................................................251
13.1.10 Select-IR-Scan...............................................................................................................................251
13.1.11 Capture-IR......................................................................................................................................252
13.1.12 Shift-IR............................................................................................................................................252
13.1.13 Exit1-IR...........................................................................................................................................252
13.1.14 Pause-IR.........................................................................................................................................252
13.1.15 Exit2-IR...........................................................................................................................................252
13.1.16 Update-IR.......................................................................................................................................252
13.2 INSTRUCTION REGISTER...........................................................................................................254
13.2.1 SAMPLE:PRELOAD..........................................................................................................................254
13.2.2 BYPASS.............................................................................................................................................254
13.2.3 EXTEST.............................................................................................................................................254
13.2.4 CLAMP...............................................................................................................................................254
13.2.5 HIGHZ................................................................................................................................................254
13.2.6 IDCODE.............................................................................................................................................254
13.3 JTAG ID CODES......................................................................................................................255
13.4 TEST REGISTERS.....................................................................................................................255
13.4.1 Boundary Scan Register....................................................................................................................255
13.4.2 Bypass Register.................................................................................................................................255
13.4.3 Identification Register.........................................................................................................................255
14. PIN CONFIGURATION.................................................................................................256
15. PACKAGE INFORMATION..........................................................................................257 15.1 64-PIN LQFP (56-G4019-001)................................................................................................257
16. DOCUMENT REVISION HISTORY...............................................................................258
DS26521 Single T1/E1/J1 Transceiver
LIST OF FIGURES Figure 6-1. Block Diagram.........................................................................................................................................17
Figure 6-2. Detailed Block Diagram...........................................................................................................................18
Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0)..............................................26
Figure 8-2. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, SPI_CPHA = 0)..............................................26
Figure 8-3. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 1)..............................................26
Figure 8-4. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, SPI_CPHA = 1)..............................................26
Figure 8-5. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 0)..............................................27
Figure 8-6. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 0)..............................................27
Figure 8-7. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 1)..............................................27
Figure 8-8. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 1)..............................................27
Figure 8-9. Backplane Clock Generation...................................................................................................................28
Figure 8-10. Device Interrupt Information Flow Diagram...........................................................................................31
Figure 8-11. IBO Example Circuit..............................................................................................................................35
Figure 8-12. RSYNC Input in H.100 (CT Bus) Mode.................................................................................................36
Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode.....................................................................37
Figure 8-14. CRC-4 Recalculate Method..................................................................................................................58
Figure 8-15. Receive HDLC Example........................................................................................................................64
Figure 8-16. HDLC Message Transmit Example.......................................................................................................66
Figure 8-17. Basic Balanced Network Connections..................................................................................................68
Figure 8-18. T1/J1 Transmit Pulse Templates..........................................................................................................71
Figure 8-19. E1 Transmit Pulse Templates...............................................................................................................72
Figure 8-20. Typical Monitor Application...................................................................................................................74
Figure 8-21. Jitter Attenuation...................................................................................................................................76
Figure 8-22. Analog Loopback...................................................................................................................................77
Figure 8-23. Local Loopback.....................................................................................................................................77
Figure 8-24. Remote Loopback.................................................................................................................................78
Figure 8-25. Dual Loopback......................................................................................................................................78
Figure 10-1. T1 Receive-Side D4 Timing................................................................................................................220
Figure 10-2. T1 Receive-Side ESF Timing..............................................................................................................220
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)...............................................................221
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................221
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................222
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode..................................................................223
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode..............................................................224
Figure 10-8. T1 Transmit-Side D4 Timing...............................................................................................................225
Figure 10-9. T1 Transmit-Side ESF Timing.............................................................................................................225
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................226
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................226
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................227
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode...............................................................228
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode....................................................................229
Figure 10-15. E1 Receive-Side Timing....................................................................................................................230
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................230
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................231
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................231
Figure 10-19. E1 Transmit-Side Timing...................................................................................................................232
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................232
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................233
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................233
Figure 10-23. E1 G.802 Timing...............................................................................................................................234
Figure 12-1. Intel Bus Read Timing (BTS = 0)........................................................................................................238
Figure 12-2. Intel Bus Write Timing (BTS = 0).........................................................................................................238
Figure 12-3. Motorola Bus Read Timing (BTS = 1).................................................................................................239
Figure 12-4. Motorola Bus Write Timing (BTS = 1).................................................................................................239
