DS2223 ,256朾it EconoRAMDS2223/DS2224DS2223/DS2224EconoRAM
DS2223 ,256朾it EconoRAMDS2223/DS2224DS2223/DS2224EconoRAM
DS2223Z ,256朾it EconoRAMDS2223/DS2224DS2223/DS2224EconoRAM
DS2224 ,32朾it serial number (ROM), 224朾it SRAMDS2223/DS2224DS2223/DS2224EconoRAM
DS2227-100 ,Flexible NV SRAM StikFEATURES PIN ASSIGNMENT Flexibly organized as 128k x 32, 256k x 16,or 512k x 8 bits Data retentio ..
DS2227-120 ,Flexible NV SRAM Stikapplications data integrity is paramount. TheDS2227 provides two batteries for each SRAM and an int ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2223-DS2224
32朾it serial number (ROM), 224朾it SRAM
DS2223/DS2224EconoRAM
DS2223/DS2224
080598 1/10
FEATURESLow–cost, general–purpose, 256–bit memoryDS2223 has 256–bit SRAMDS2224 has 32–bit ROM, 224–bit SRAMReduces control, address and data interface to a
single pinEach DS2224 32–bit ROM is factory–lasered with a
unique serial numberDS2224 portion of ROM with custom code and unique
serial number availableMinimal operating power: 45 nanocoulombs per
transaction @1.5V typicalLess than 15 nA standby current at 25°CNonvolatile data retention easily achieved via low–
cost alkaline batteries or capacitorsDirectly connects to a port pin of popular microcontrol-
lersOperation from 1.2 to 5.5 voltsPopular TO–92 or SOT–223 surface mount packageOperates over industrial temperature range –40°C to
+85°C
DESCRIPTIONThe DS2223 and DS2224 EconoRAMs are fully static,
micro–powered, read/write memories in low–cost
TO–92 or SOT–223 packages. The DS2223 is orga-
nized as a serial 256 x 1 bit static read/write memory.
The DS2224’s first 32 bits are lasered with a unique ID
code at the time of manufacture; the remaining 224 bits
are static read/write memory. Signaling necessary for
reading or writing is reduced to just one interface lead.
Both the DS2223 and DS2224 are not recommended
for new designs. However, the parts will remain avail-
able until the year 2003, at least.
PACKAGE OUTLINE3234
SOT–223
TOP VIEWBOTTOM VIEW
TO–92
See Mech. DrawingsSectionSee Mech. DrawingsSection
PIN CONNECTIONSPin 1GND–Ground
Pin 2DQ–Data In/Out
Pin 3VCC–Supply
Pin 4GND–Ground
ORDERING INFORMATIONDS2223256–bit SRAM – TO–92 Package
DS2223Z256–bit SRAM – SOT–223 Package
DS2223T1000 piece tape–and–reel of DS2223
DS2223Y2500 piece tape–and–reel of DS2223Z
DS222432–bit serial number (ROM), 224–bit
SRAM – TO–92 Package
DS2224Z32–bit serial number (ROM), 224–bit
SRAM – SOT–223 Package
DS2224T 1000 piece tape–and–reel of DS2224
DS2224Y2500 piece tape–and–reel of DS2224Z
DS2223/DS2224
080598 2/10
OPERATIONAll communications to and from the EconoRAM are
accomplished via a single interface lead. EconoRAM
data is read and written through the use of time slots. All
data is preceded by a command byte to specify the type
of transaction. Once a specific transaction has been
initiated, either a read or a write, it must be com-
pleted for all memory locations before another
transaction can be started.
1–WIRE SIGNALLINGThe EconoRAM requires strict protocols to insure data
integrity. The protocol consists of three types of signal-
ling on one line: Write 0 time slot, Write 1 time slot and
Read Data time slot. All these signals are initiated by the
host.
READ/WRITE TIME SLOTSThe definitions of write and read time slots are illustrated
in Figures 1 through 3. All time slots are initiated by the
host driving the data line low. The falling edge of the data
line synchronizes the EconoRAM to the host by trigger-
ing a delay circuit in the EconoRAM. During write time
slots, the delay circuit determines when the EconoRAM
will sample the data line. For a read data time slot, if a “0”
is to be transmitted, the delay circuit determines how
long the EconoRAM will hold the data line low overriding
the 1 generated by the host. If the data bit is a “1”, the
EconoRAM will leave the read data time slot
unchanged.
COMMAND BYTEThe command byte to specify the type of transaction is
transmitted LSB first from the host to the EconoRAM
using write time slots. The first bit of the command byte
(see Figure 4) is a logic 1. This indicates to the Econo-
RAM that a command byte is being written. The next two
bits are the select bits which denote the physical
address of the EconoRAM that is to be accessed (set to
00 currently). The remaining five bits determine whether
a read or a write operation is to follow. If a write operation
is to be performed, all five bits are set to a logic 1 level. If
a read operation is to be performed, any or all of these
bits are set to a logic 0 level. All eight bits of the com-
mand byte are transmitted to the EconoRAM with a sep-
arate time slot for each bit.
READ OR WRITE TRANSACTIONRead or write transactions are performed by initializing
the EconoRAM to a known state, issuing a command
byte, and then generating the time slots to either read
EconoRAM contents or write new data. Each transac-
tion consists of 264 time slots. Eight time slots transmit
the command byte, the remaining 256 time slots trans-
fer the data bits. (See Figure 5.) Once a transaction is
started, it must be completed before a new transaction
can begin.
To initially set the EconoRAM into a known state, 264
Write Zero time slots must be sent by the host. These
Write Zero time slots will not corrupt the data in the Eco-
noRAM since a command byte has not been written.
This operation will increment the address pointer inter-
nal to the EconoRAM to its maximum count value. Upon
reaching this maximum value, the EconoRAM will
ignore all additional Write Zero time slots issued to it and
the internal address pointer will remain locked at the top
count value. This condition is removed by the reception
of a Write One time slot, typically the first bit of a com-
mand byte.
Once the EconoRAM has been set into a known state,
the command byte is transmitted to the EconoRAM with
eight write time slots. This resets the address pointer
internal to the EconoRAM and prepares it for the
appropriate operation, either a read or a write.
After the command byte has been received by the Eco-
noRAM, the host controls the transfer of data. In the
case of a read transaction, the host issues 256 read time
slots. In the case of a write transaction, the host issues
256 write time slots according to the data to be written.
All data is read and written least significant bit first.
Although the DS2224 has the first 32 bits replaced by
lasered ROM rather than SRAM, it requires 256 write
time slots for a complete write transaction. The data
being sent during the first 32 write time slots has no
effect on the DS2224 other than advancing the internal
address pointer. As stated previously, it is not possible
to change from read to write or vice versa before a trans-
action is completed.
DS2223/DS2224
080598 3/10
READ/WRITE TIMING DIAGRAM
Write–One Time Slot Figure 1VPULLUPVPULLUP MIN
VIH MIN
VIL MAX
60 μs < tSLOT <
1 μs < tLOW1 < 15 μs
1 μs < tREC <
Write–Zero Time Slot Figure 2VPULLUPVPULLUP MINVIH MIN
VIL MAX
tREC
60 μs < tLOW0 < tSLOT <
1 μs < tREC <
Read–Data Time Slot Figure 3VPULLUPVPULLUP MIN
VIH MIN
VIL MAX
60 μs < tSLOT <
1 μs < tLOWR < 15 μs
0 < tRELEASE < 45 μs
1 μs < tREC <
tRDV = 15 μs
DS2223/DS2224
080598 4/10
COMMAND WORD Figure 4MSBLSB
ALL 1s – WRITE
ANY 0 – READ
SELECT BITS
READ/WRITE TRANSACTION Figure 5READ/WRITE FLOW
8 BITSDS2223
DS2224
LSB
DS2223/DS2224
080598 5/10
TYPICAL CURRENT CONSUMPTION VS. BIT RATE Figure 610 μA
1 μA
100 nA
10 nA
5 nA
10 bps100 bps1 kbps10 kbps
BIT RATE
CURRENT
CONSUMPTION
TYPICAL LEAKAGE CURRENT VS. TEMPERATURE Figure 7–100+10+20+30+40+50+60+70
TEMPERATURE (DEG. C)
NANOAMPS
LEAKAGE CURRENT
DS2223/DS2224
080598 6/10
1–WIRE INTERFACEThe 1–Wire interface has only a single line by definition;
it is important that host and EconoRAM be able to drive it
at the appropriate time. The EconoRAM is an open drain
part with an internal circuit equivalent to that shown in
Figure 8. The host can be the same equivalent circuit. If
a bidirectional pin is not available, separate output and
input pins can be tied together.
The 1–Wire interface requires a pull–up resistor with a
value of approximately 5 kΩ to system VCC on the data
signal line. The EconoRAM has an internal open–drain
driver with a 500 kΩ pull–down resistor to ground. The
open–drain driver allows the EconoRAM to be powered
by a small standby energy source, such as a single 1.5
volt alkaline battery, and still have the ability to produce
CMOS/TTL output levels. The pull–down resistor holds
the DQ pin at ground when the EconoRAM is not con-
nected to the host.
APPLICATION EXAMPLESEconoRAMs are extremely conservative with power.
Data can be retained in these small memories for as
long as a month using the energy stored in a capacitor.
Data is retained as long as the voltage on the VCC pin of
the EconoRAM (VCAP) is at least 1.2 volts. A typical cir-
cuit is shown in Figure 9.
When VCC is applied, capacitor C1 is charged and the
EconoRAM receives power directly from VCC. After
power is removed, the diode CR1 prevents current from
leaking back into the system, keeping the capacitor
charged.
In the standby mode, the EconoRAM typically con-
sumes only 12 nA at 25°C. However, the power–down
process of the system can cause a slightly higher cur-
rent drain. This is due to the fact that as system power
ramps down, the signal attached to the DQ pin of the
EconoRAM transitions slowly through the linear region,
while the VCAP voltage remains at its initial value. While
in this region, the part draws more current as a function
of the DQ pin voltage (see Figure 10).
The data retention time can be estimated with the aid of
Figure 11. In this figure, the vertical axis represents the
value of the capacitor C1; the horizontal axis is the data
retention time in hours. The two curves represent initial
on the assumption that the time the DQ pin is in the lin-
ear region is less than 100 ms.
HOST TO ECONORAM INTERFACE Figure 8
