DS2175 ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
DS2175S ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
DS2176 ,T1 Receive BufferPIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 I Signaling Inhibit. When low, ABCD signaling u ..
DS2176N ,T1 Receive BufferFEATURES PIN ASSIGNMENT§ Synchronizes loop–timed and system–timedT1 data streamsSIGH 1 24 VDDRMSYN2 ..
DS2176Q ,T1 Receive BufferPIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 I Signaling Inhibit. When low, ABCD signaling u ..
DS2176Q+ ,T1 Receive BufferFEATURES PIN ASSIGNMENT§ Synchronizes loop–timed and system–timedT1 data streamsSIGH 1 24 VDDRMSYN2 ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2175
T1/CEPT Elastic Store
FEATURESRate buffer for T1 and CEPT transmission
systems· Synchronizes loop–timed and system timed
data streams on frame boundariesIdeal for T1 (1.544 MHz) to CEPT (2.048
MHz), CEPT to T1 interfaces· Supports parallel and serial backplanesBuffer depth is 2 framesComprehensive on–chip “slip” control logic– Slips occur only on frame boundaries
– Outputs report slip occurrences and
direction
– Align feature allows buffer to be recentered
at any time– Buffer depth easily monitoredCompatible with DS2180A T1 and DS2181A
CEPT TransceiversIndustrial temperature range of –40°C to
+85°C available, designated DS2175N
PIN ASSIGNMENT
DESCRIPTIONThe DS2175 is a low–power CMOS elastic–store memory optimized for use in primary rate telecommu-
nications transmission equipment. The device serves as a synchronizing element between async data
streams and is compatible with North American (T1–1.544 MHz) and European (CEPT–2.048 MHz) ratenetworks. The chip has several flexible operating modes which eliminate support logic and hardware cur-
rently required to interconnect parallel or serial TDM backplanes. Application areas include digital
trunks, drop and insert equipment, digital cross–connects (DACS), private network equipment and
PABX–to–computer interfaces such as DMI and CPI.
T1/CEPT Elastic StoreVDD
SYSCLK
SFSYNC
SSER
SCHCLK
S/P
SCLKSEL
RCLKSEL
RCLK
RSER
RMSYNC
FSD
SLIP
VSS
ALN
SMSYNC
DS2175
DS2175 BLOCK DIAGRAM Figure 1
DS2175
PIN Description Table 1
PCM BUFFERThe DS2175 utilizes a 2–frame buffer to synchronize in-coming PCM data to the system backplane clock.
Buffer depth is mode–dependent; 2.048 MHz to 2.048 MHz applications utilize 64 bytes of buffer
memory, while all other modes are supported by 48 bytes. The buffer samples data at RSER on the fallingedge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer
depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is completely
emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always occur on frame
boundaries.
DATA FORMATData is presented to, and output from, the elastic store in a “framed” format. A rising edge at RMSYNCand SFSYNC establishes frame boundaries for the receive and system sides. North American (T1) frames
contain 24 data channels of 8 bits each and an F–bit (193 bits total). European (CEPT) frames contain 32
data channels (256 bits). The frame rate of both systems is 8 KHz. RMSYNC and SFSYNC do not
require a pulse at every frame boundary; if desired, they may be pulsed once to establish frame alignment.
Internal counters will then maintain the frame alignment and may be reinforced by the next rising edge atRMSYNC and/or SFSYNC.
DS2175
SLIP CORRECTION CAPABILITYThe 2–frame buffer depth is adequate for T–carrier and CEPT applications where short term jitter
synchronization, rather than correction of significant frequency differences, is required. The DS2175
provides an ideal balance between total delay (less than 250 microse-conds at its full depth) and slip
correction capability.
BUFFER RECENTERINGMany applications require that the buffer be recentered during system power–up and/or initialization.
Forcing ALN low recenters the buffer on the occurrence of the next frame sync boundary. A slip will
occur during this recentering if the buffer depth is adjusted. If the depth is presently optimum, noadjustment (slip) occurs.
SLIP REPORTINGSLIP is held low for 65 SYSCLK cycles when a slip occurs. SLIP is an active–low, open collector
output. FSD indicates slip direction. When low (buffer empty) a frame of data was “repeated” at SSER
during the previous slip. When high (buffer full), a frame of data was “deleted”. FSD is updated at every
slip occurrence.
BUFFER DEPTH MONITORINGSMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance
between rising edges of RMSYNC and SMSYNC indicates the current buffer depth. Impending slip
conditions may be determined by monitoring RMSYNC and SMSYNC real time. SMSYNC is held high
for 65 SYSCLK periods.
CLOCK SELECTReceive and system side clock frequencies are independently selectable by inputs RCLKSEL and
SCLKSEL. 1.544 MHz is selected when RCLKSEL (SCLKSEL) = 0; 2.048 MHz is selected when
RCLKSEL (SCLKSEL) = 1. In 1.544 MHz (receive) to 1.544 MHz (system) applications, the F-bit
position is passed through the receive buffer and presented at SSER immediately after the rising edge of
the system side frame sync. The F–bit position is forced to 1 in 2.048 MHz to 1.544 MHz applications.No F–bit position exists in 2.048 MHz system side applications.
PARALLEL COMPATIBILITYThe DS2175 is compatible with parallel and serial backplanes. Channel 1 data appears at SSER after a
rising edge at SFSYNC (serial applications, S/
applications (S/a parallel format requires an HC595 shift register.
DS2175
RECEIVE SIDE TIMING (RCLK = 1.544 MHz) Figure 2
RECEIVE SIDE TIMING (RCLK = 2.048 MHz) Figure 3
NOTES:1. All channel data is passed through the elastic store in 2.048 MHz system side applications
(SCLKSEL = 1);
2. Data in channels >24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0).
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 4
NOTES:1. In 1.544 MHz receive side applications (RCLKSEL=0), the F–bit position contains F–bit data
extracted from the data stream at RSER. The F–bit position is forced to “1” in 2.048 MHz receiveside applications (RCLKSEL=1).
2. In 2.048 MHz receive side applications (RCLKSEL=1), the E–bit position is forced to “1” and data in
DS2175
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 2.048 MHz) Figure 5
NOTES:1. In 2.048 MHz receive side applications (RCLKSEL=1), all channel data is passed through the elastic
store.
2. In 1.544 MHz receive side applications (RCLKSEL=0), all channel data is passed through the elastic
store, except the F–bit position which is ignored. Data in channels >24 on the system side is forced toall ones.
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.
