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DS1862DALLASN/a1100avaiXFP Laser Control and Digital Diagnostic IC
DS1862B+MAIXMN/a1500avaiXFP Laser Control and Digital Diagnostic IC


DS1862B+ ,XFP Laser Control and Digital Diagnostic ICFeaturesThe DS1862 is a closed-loop laser-driver control IC with ♦ Implements XFP MSA Requirements ..
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DS1862-DS1862B+
XFP Laser Control and Digital Diagnostic IC
General Description
The DS1862 is a closed-loop laser-driver control IC with
built-in digital diagnostics designed for XFP MSA. The
laser control function incorporates automatic power
control (APC) and allows extinction ratio control though
a temperature-indexed lookup table (LUT). The DS1862
monitors up to seven analog inputs, including tempera-
ture and monitor diode (MD) current, which are used to
regulate the laser bias current and extinction ratio.
Warning and alarm thresholds can be programmed to
generate an interrupt if monitored signals exceed toler-
ance. Calibration is also provided internally using inde-
pendent gain and offset scaling registers for each of
the monitored analog signals. Settings such as pro-
grammed calibration data are stored in password-pro-
tected EEPROM memory. Programming is accomplished
through an I2C-compatible interface, which can also be
used to access diagnostic functionality.
Applications

Laser Control and Monitoring 10Gbps Optical
Transceiver Modules (XFP)
Laser Control and Monitoring
Digital Diagnostics in Optical Transmission
Features
Implements XFP MSA Requirements for Digital
Diagnostics, Serial ID, and User Memory
I2C-Compatible Serial InterfaceAutomatic Power Control (APC)Extinction Ratio Control with Lookup TableSeven Monitored Channels for Digital Diagnostics
(Five Basic Plus Two Auxiliary)
Internal Calibration of Monitored Channels
(Temp, VCC2/3, Bias Current, Transmitted, and
Received Power)
Programmable Quick-Trip Logic for Turning
Off Laser for Eye Safety
Access to Monitoring and ID InformationProgrammable Alarm and Warning ThresholdsOperates from 3.3V or 5V Supply25-Ball CSBGA, 5mm x 5mm PackageInternal or External Temperature Sensor-40°C to +100°C Operating Temperature RangeOne 8-Bit Buffered DAC
DS1862
XFP Laser Control and Digital Diagnostic IC
CSBGA (5mm x 5mm)

TOP VIEW4235
P-DOWN/
RSTSC-RX-LOSSC-RX-LOLTHRSET
RSSIMODSETSCLRX-LOSFETG
EN2BIASSETSDATX-DEN1
AUX2MONBMDMOD-NRINTERRUPTAUX1MON
SC-TX-LOSVCC3MOD-DESELGNDIBIASMON
VCC2
Pin Configuration

Rev 1; 12/07
+Denotes a lead-free/RoHS-compliant package.
Ordering Information
Typical Operating Circuit appears at end of data sheet.
PARTTEMP RANGEPIN-PACKAGE

DS1862B -40°C to +100°C 25 CSBGA
DS1862B+ -40°C to +100°C 25 CSBGA
DS1862
XFP Laser Control and Digital Diagnostic IC
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS

(VCC3= +2.9V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on Any Open-Drain Pin
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on MOD-DESEL, SDA, SCL,
FETG, THRSET, TX-D, AUX1MON, AUX2MON,
IBIASMON, RSSI, BIASSET, MODSET,
EN1, EN2............................................-0.5V to (VCC3+ 0.5V)*
Voltage Range on SC-RX-LOS,
SC-RX-LOL, RX-LOS, SC-TX-LOS,
MOD-NR, EN1, EN2...........................-0.5V to (VCC2+ 0.5V)*
Operating Temperature Range.........................-40°C to +100°C
EEPROM Programming Temperature Range.........0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC JEDEC
J-STD-020 Specification.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Main Supply Voltage VCC3 (Note 1) +2.9 +5.5 V
Secondary Supply Voltage VCC2 VCC2 not to exceed VCC3 (Note 2) +1.6 +3.6 V
High-Level Input Voltage
(SDA, SCL) VIH IIH (max) = 10μA 0.7 x
VCC3
VCC3 +
0.5 V
Low-Level Input Voltage
(SDA, SCL) VIL IIL (max) = -10μA GND -
0.3
0.3 x
VCC3V
High-Level Input Voltage
(TX-D, MOD-DESEL,
P-DOWN/RST) (Note 3)
VIH IIH (max) = 10μA 2 VCC3 +
0.3 V
Low-Level Input Voltage
(TX-D, MOD-DESEL,
P-DOWN/RST) (Note 3)
VIL IIL (max) = -10μA -0.3 +0.8 V
*Not to exceed +6.0V.
DS1862
XFP Laser Control and Digital Diagnostic IC
DC ELECTRICAL CHARACTERISTICS

(VCC3= +2.9V to +5.5V, VCC2= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Supply Current ICC3 P-DOWN/RST = 1 3 5 mA
High-Level Output Voltage
(FETG) VOH IOH (max) = -2mA VCC3 -
0.5 V
Low-Level Output Voltage
(MOD-NR, INTERRUPT, SDA,
FETG)
VOL IOL (max) = 3mA 0 0.4 V
Resistor (Pullup) RPU 912 15k
I/O Capacitance CI/O (Note 4) 10 pF
Leakage Current IL -10 +10 μA
Leakage Current (SCL, SDA) IL -10 +10 μA
Digital Power-On Reset POD 1.0 2.2 V
Analog Power-On Reset POA 2.0 2.6 V
DC ELECTRICAL CHARACTERISTICS—INTERFACE SIGNALS TO SIGNAL CONDITIONERS

(VCC2= +1.6V to +3.6V, VCC3= +2.9V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

High-Level Input Voltage
(SC-RX-LOS, SC-RX-LOL,
SC-TX-LOS)
VIH IIH (max) = 100μA 0.7 x
VCC2
VCC2 +
0.1 V
Low-Level Input Voltage
(SC-RX-LOS, SC-RX-LOL,
SC-TX-LOS)
VIL IIL (max) = -100μA 0 0.3 x
VCC2V
VOH IOH (max) = -0.7mA VCC2 -
0.2
VOH2 VCC2 = 2.5V to 3.6V, IOH (max) = -2mA VCC2 -
0.4
High-Level Output Voltage
(EN1, EN2)
VOH3 VCC2 = 1.6V, IOH (max) = -0.7mA VCC2 -
0.2
VOL IOL (max) = 0.7mA 0.20 Low-Level Output Voltage
(EN1, EN2, RX-LOS) VOL2 VCC2 = 2.5V to 3.6V, IOL (max) = 2mA 0.40 V
Leakage Current
(SC-RX-LOS, SC-RX-LOL,
SC-TX-LOS, RX-LOS)
IL -10 +10 μA
DS1862
XFP Laser Control and Digital Diagnostic IC
I2C AC ELECTRICAL CHARACTERISTICS

(VCC3= +2.9V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

SCL Clock Frequency fSCI 0 400 kHz
Clock Pulse-Width Low tLOW 1.3 μs
Clock Pulse-Width High tHIGH 0.6 μs
Bus Free Time Between STOP
and START Conditions tBUF 1.3 μs
START Hold Time tHD:SDA 0.6 μs
START Setup Time tSU:SDA 0.6 μs
Data In Hold Time tHD:DAT 0 0.9 μs
Data In Setup Time tSU:DAT 100 ns
Rise Time of Both SDA and
SCL Signals tR (Note 5) 20 +
0.1CB 300 ns
Fall Time of Both SDA and
SCL Signals tF (Note 5) 20 +
0.1CB 300 ns
STOP Setup Time tSU:STO 0.6 μs
MOD-DESEL Setup Time tHOST_SELECT_SETUP 2 ms
MOD-DESEL Hold Time tHOST_SELECT_HOLD 10 μs
Aborted Sequence Bus Release tMOD-DESEL_ABORT 2 ms
Capacitive Load for Each Bus CB (Note 5) 400 pF
EEPROM Write Time tW 4-byte write (Note 6) 16 ms
ANALOG OUTPUT CHARACTERISTICS

(VCC3= +2.9V to +5.5V, VCC2= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

IBIASSET IBIASSET 0.01 1.50 mA
IBIASSET (Off-State Current) IBIASSET Shutdown ±10 ±100 nA
IMODSET IMODSET 0.01 1.20 mA
IMODSET (Off-State Current) IMODSET Shutdown ±10 ±100 nA
Voltage on IBIASSET and IMODSET VMAX (Note 7) 0.7 3.0 V
VTHRSET VTHRSET IMAX = 100μA 50 1000 mV
VTHRSET Drift Across temperature (Note 8) -5 +5 %
VTHRSET Capacitance Load CTHRSET 1 nF
APC Calibration Accuracy +25°C 25 μA
0.200mA to 1.5mA -5 +5 % APC Temp Drift 50μA to 200μA 12 μA
Sink, SRC_SINK_B = 0 -0.9 +0.9 IBMD DNL Source, SRC_SINK_B = 1 -0.9 +0.9 LSB
Sink, SRC_SINK_B = 0 -4.0 +4.0 IBMD INL Source, SRC_SINK_B = 1 -4.0 +4.0 LSB
IBMD Voltage Drift 1.2 %/V
IBMD FS Accuracy 1.5 %
DS1862
XFP Laser Control and Digital Diagnostic IC
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Time to Initialize tINIT VCC3 within ±5% of nominal 30 200 ms
TX-D Assert Time tOFF IBIAS and IMOD below 10% of nominal 5 μs
TX-D Deassert Time tON IBIAS and IMOD above 90% of nominal 1 ms
P-DOWN/RST Assert Time tPDR-ON IBIAS and IMOD below 10% of nominal 100 μs
P-DOWN/RST Deassert Time tPDR-OFF IBIAS and IMOD above 90% of nominal 200 ms
MOD-DESEL Deassert Time tMOD-DESELTime until proper response to I2C
communication 2 ms
INTERRUPT Assert Delay tINIT_ON Time from fault to interrupt assertion 100 ms
INTERRUPT Deassert Delay tINIT_OFFTime from read (clear flags) to interrupt
deassertion 500 μs
MOD-NR Assert Delay tMOD-NR-ON Time from fault to MOD-NR assertion 0.5 ms
MOD-NR Deassert Delay tMOD-NR-OFFTime from read (clear flags) to MOD-NR
deassertion 0.5 ms
RX-LOS Assert Time tLOS-ONTime from SC-RX-LOS assertion to
RX-LOS assertion 100 ns
RX-LOS Deassert Time tLOS-OFFTime from SC-RX-LOS deassertion to
RX-LOS deassertion 100 ns
P-DOWN/RST Reset Time tRESETTime from P-DOWN/RST assertion to
initial reset 10 μs
Shutdown Time tFAULTTime from fault to IBIASSET, IMODSET,
and IBMD below 10% 30 μs
ANALOG OUTPUT CHARACTERISTICS (continued)

(VCC3= +2.9V to +5.5V, VCC2= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

IMODSET Accuracy +25°C, IMODSET = 0.04mA to 1.2mA -1.5 +1.5 %
75μA range -0.9 +0.9
150μA range -0.9 +0.9
300μA range -0.9 +0.9
600μA range -0.9 +0.9
IMODSET DNL
1200μA range -0.9 +0.9
LSB
75μA range -1.5 +1.5
150μA range -1.5 +1.5
300μA range -1.0 +1.0
600μA range -1.0 +1.0
IMODSET INL
1200μA range -1.0 +1.0
LSB
IMODSET Temp Drift 5 %
IMODSET Voltage Drift 1.2 %/V
IMODSET FS Accuracy 1.5 %
APC Bandwidth IMD / IAPC = 1 (Note 4) 6 10 30 kHz
AC ELECTRICAL CHARACTERISTICS—XFP CONTROLLER

(VCC3= +2.9V to +5.5V, VCC2= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
DS1862
XFP Laser Control and Digital Diagnostic IC
AC ELECTRICAL CHARACTERISTICS—SOFT* CONTROL AND STATUS

(VCC3= +2.9V to +5.5V, VCC2= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

SOFT TX-D Assert Time tOFF_SOFT IBIAS and IMOD below 10% of nominal 50 ms
SOFT TX-D Deassert Time tON_SOFT IBIAS and IMOD above 90% of nominal 50 ms
SOFT P-DOWN/RST Assert Time tPDR-ON_SOFT IBIAS and IMOD below 10% of nominal 50 ms
SOFT P-DOWN/RST Deassert Time tPDR-OFF_SOFT IBIAS and IMOD above 90% of nominal 200 ms
Soft MOD-NR Assert Delay tMOD-NR-ON
_SOFTTime from fault to MOD-NR assertion 50 ms
Soft MOD-NR Deassert Delay tMOD-NR-OFF
_SOFT
Time from read (clear flags) to MOD-NR
deassertion 50 ms
Soft RX_LOS Assert Time tLOS-
ON_SOFT
Time from SC-RX-LOS assertion to
RX-LOS assertion 50 ms
Soft RX_LOS Deassert Time tLOS-
OFF_SOFT
Time from SC-RX-LOS deassertion to
RX-LOS deassertion 50 ms
Analog Parameter Data Ready
(DATA-NR) 500 ms
*All SOFT timing specifications are measured from the falling edge of STOP signal during I2C communication.
ANALOG INPUT CHARACTERISTICS

(VCC3= +2.9V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

IBMD Configurable Source or
Sink (+/-) 0.05 1.50 mA
Source mode 2.0 IBMD Voltage (IBMD - 0μA) VBMDSink mode IBMD range 0 to 1.5mA 1.2 V
IBMD Input ResistanceRBMD 400 550 700 
A/D INPUT VOLTAGE MONITORING (IBIASMON, AUX2MON, AUX1MON, RSSI, BMD)

(VCC3= +2.9V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Input Resolution VMON 610 μV
Supply Resolution VCC2/3 1.6 mV
Input/Supply Accuracy ACC At factory setting 0.25 0.5 %FS
tFRAME1 AUX1MON and AUX2MON disabled 48 52 Update Rate tFRAME2 All channels enabled 64 75 ms
Input/Supply Offset VOS (Note 4) 0 5 LSB
Full-Scale Input (IBIASMON and
RSSI) At factory setting 2.4875 2.5 2.5125 V
Full-Scale Input (AUX1MON,
AUX2MON, VCC2, VCC3)
At factory setting
(Note 9) 6.5208 6.5536 6.5864 V
BMD (Monitor) (TX-P) FS setting 1.5 mA
DS1862
XFP Laser Control and Digital Diagnostic IC
FAST ALARMS AND VCCFAULT CHARACTERISTICS

(VCC3= +2.9V to +5.5V, VCC2= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

HIGH BIAS and TX-P Threshold
FS (Note 10) 2.48 2.5 2.52 mA
VCC2/3 Fault Asserted
Falling Edge Delay
 VCC2/3
(Note 11) 75 ms
QT Temperature Coefficient -3 +3 %
QT Voltage Coefficient 0.5 %/V
QT FS Trim Accuracy (4.2V,
+25°C) 2.480 2.500 2.520 mA
QT Accuracy (Trip) (INL) -2 0 +2 LSB
QT Voltco 0.5 %/V
QT Tempco 1.5 3 %
Note 1:
All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2:
Secondary power supply is used to support optional variable power-supply feature of the XFP module. If VCC2is not used
(i.e., signal conditioners using 3.3V supply), VCC2should be connected to the VCC3.
Note 3:
Input signals (i.e., TX-D, MOD-DESEL, and P-DOWN/RST) have internal pullup resistors.
Note 4:
Guaranteed by design. Simulated over process and 50μA < IBMD< 1500μA.
Note 5:
CB—total capacitance of one bus line in picofarads.
Note 6:
EEPROM write begins after a STOP condition occurs.
Note 7:
This is the maximum and minimum voltage on the MODSET and BIASSET pins required to meet accuracy and drift specifi-
cations.
Note 8:
For VTHRSET, offset may be as much as 10mV.
Note 9:
This is the uncalibrated offset provided by the factory; offset adjustment is available on this channel.
Note 10:
%FS refers to calibrated FS in case of internal calibration, and uncalibrated FS in the case of external calibration.
Uncalibrated FS is set in the factory and specified in this data sheet as FS (factory). Calibrated FS is set by the user, allow-
ing a change in any monitored channel scale.
Note 11:
See the Monitor Channelssection for more detail or VCC2and VCC3selection.
NONVOLATILE MEMORY CHARACTERISTICS

(VCC3= +2.9V to +5.5V, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Endurance (Write Cycle) +70°C 50k Cycles
Endurance (Write Cycle) +25°C 200k Cycles
DS1862
XFP Laser Control and Digital Diagnostic IC
Timing Diagrams

VCC > VPOA
TX-D
IBIASSET
IMODSET
tINIT
P-DOWN/RST
INTERRUPT
RESET
-DONE
RESET
-DONE
READ-FLAGS
tINIT_ON
tPDR-OFF
tINIT_OFFtINIT
READ-FLAGS
Figure 1. Power-On Initialization with P-DOWN/RST Asserted and TX-D/SOFT TX-D Not Asserted
Figure 2. Power-On Initialization with P-DOWN/RST Not Asserted and TX-D/SOFT TX-D Not Asserted (Normal Operation)
VCC > VPOA
TX-D
IBIASSET
IMODSET
tINIT
P-DOWN/RST
INTERRUPT
tINIT_ONtINIT_OFF
READ-FLAGS
RESET
-DONE
DS1862
XFP Laser Control and Digital Diagnostic IC
Timing Diagrams (continued)

TX-D
TX-F
IBIASSET
IMODSET
tOFFtON
Figure 3. TX-D Timing During Normal Operation
Figure 4. Detection of Safety Fault Condition
TX-D
FETG
OCCURRENCE
OF FAULT
IBIASSET
IMODSET
tFAULT
DS1862
XFP Laser Control and Digital Diagnostic IC

FETG
P-DOWN/RST
OCCURRENCE
OF FAULT
IBIASSET
IMODSET
tRESET
tINIT
RESET-DONE
Figure 5. Successful Recovery from Transient Safety Fault Condition Using P-DOWN/RST
Figure 6. Unsuccessful Recovery from Transient Safety Fault Condition
FETG
(FETG_POL = 1)
P-DOWN/RST
OCCURRENCE
OF FAULT
IBIASSET
IMODSET
tRESET
tFAULT
tFAULT
RESET
-DONE
Timing Diagrams (continued)
DS1862
XFP Laser Control and Digital Diagnostic IC

READ FLAGS
OCCURRENCE
OF MONITOR
CHANNEL FAULTtINIT_ON
tINIT_OFF
INTERRUPT
Figure 7. Monitor Channel Fault Timing
Timing Diagrams (continued)
DS1862
XFP Laser Control and Digital Diagnostic IC
Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE

DS1862 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SRC_SINK_B = 1
SRC_SINK_B = 0
IBMD = 499.479μA
SUPPLY CURRENT vs. TEMPERATURE

DS1862 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)60-151035
SRC_SINK_B = 1
SRC_SINK_B = 0
IBMD = 499.479μAVCC3 = 5.5V, VCC2 = 1.6V
IBMD DRIFT vs. TEMPERATURE

DS1862 toc03
TEMPERATURE (°C)
IBMD
DRIFT (%)60-151035
SRC_SINK_B = 1
SRC_SINK_B = 0
IBMD = 499.479μAVCC3 = 5.5V, VCC2 = 1.6V
IBMD DRIFT vs. SUPPLY VOLTAGE

DS1862 toc04
SUPPLY VOLTAGE (V)
IBMD
DRIFT (%)
SRC_SINK_B = 1
SRC_SINK_B = 0
IBMD = 499.479μA
IMODSET DRIFT vs. TEMPERATURE

DS1862 toc05
TEMPERATURE (°C)
IMODSET
DRIFT (%)-15103560
IBMD = 499.479μAVCC3 = 5.5V, VCC2 = 1.6V
INTEGRAL NONLINEARITY
OF QUICK TRIPS

DS1862 toc06
CODE (0–255)
ERROR (LSB)
DIFFERENTIAL NONLINEARITY
OF IMODSET
DS1862 toc07
CODE (0–255)
ERROR (LSB)
FSR = 75μAVCC3 = 4.2V, VCC2 = 1.6V
INTEGRAL NONLINEARITY
OF IMODSET

DS1862 toc08
CODE (0–255)
ERROR (LSB)
FSR = 75μAVCC3 = 4.2V, VCC2 = 1.6V
DS1862
XFP Laser Control and Digital Diagnostic IC
Pin Description
NAMEPINFUNCTION

P-DOWN/RST A1 Power-Down/Reset Input. This multifunction pin is pulled high internally. See the Power-Down/Reset Pin
section for additional information.
SC-RX-LOS A2 Signal Conditioner Receiver Loss-of-Signal Input. This pin is an active-high input with LVCMOS/LVTTL
voltage levels.
SC-RX-LOL A3 Signal Conditioner Receiver Loss-of-Lock Input. This pin is an active-high input with LVCMOS/LVTTL
voltage levels.
THRSET A4 Threshold Set Output. This pin is a programmable voltage source that can be used for Rx signal
conditioner.
VCC2 A5 1.8V Power-Supply Input
RX-LOS B1 Receiver Loss of Signal. This open-drain output indicates when there is insufficient optical power.
SCL B2 I2C Serial-Clock Input
FETG B3 FET Gate Output. This pin can drive an external FET gate associated with safety fault disconnect.
RSSI B4 Received Power Signal Input
MODSET B5 Modulation Current Output. This pin is only capable of sinking current.
TX-D C1 Transmit Disable Input. This pin has an internal pullup resistor.
SDA C2 I2C Serial-Data Input/Output
EN1 C3 Enable 1 Output. Functional control for signal conditioners.
EN2 C4 Enable 2 Output. Functional control for signal conditioners.
BIASSET C5 Bias Current Output. This pin is only capable of sinking current.
INTERRUPT D1 Interrupt. This open-drain output pin indicates a possible operational fault or critical status condition to
the host.
MOD-NR D2 Indicating Module Operational Fault. Open-drain output. This pin indicates the status of the MOD-NR flag.
AUX1MON D3 Aux1 Monitor Input. This pin can be used to measure any voltage quantity.
AUX2MON D4 Aux2 Monitor Input. This pin can be used to measure any voltage quantity or external temperature
BMD D5 Monitor Diode Current Input. This pin is capable of sourcing or sinking current.
GND E1 Ground
MOD-DESEL E2 Module Deselect Input. This pin must be pulled low to enable I2C communication. This pin is pulled high
internally.
IBIASMON E3 Bias Monitor Input. This pin can be used to monitor the voltage across the laser.
SC-TX-LOS E4 Signal Conditioner Transmitter Loss of Signal. This pin is an active-high input with LVCMOS/LVTTL
voltage levels.
VCC3 E5 3.3V or 5V Power-Supply Input
DS1862
XFP Laser Control and Digital Diagnostic IC
Block Diagram

MUX
VCC2
TX-P
LOGIC
SDA
SCL
MOD-DESEL
IBIASMON
RSSI
BMD
AUX1MON
ALARM AND
WARNING
THRESHOLDS
ALARM AND
WARNING
THRESHOLDS
INTERRUPT
WARNING
FLAGS
ALARM
FLAGS
EN1
EN2
RX-LOS
SC-TX-LOS
SC-RX-LOL
SC-RX-LOS
VCC3
VCC2
VCC3
VCC2
AUX2MON
TX-PIBMD
TX-P
HIGH BIAS ALARM THRESHOLD
HIGH TX_P ALARM THRESHOLD
LOW TX_P ALARM THRESHOLD
IBIASSET
BIAS AND MOD
ENABLE
TX-F
STARTUP
INITIALIZATION
AND
LASER SAFETY
SHUTDOWN
BLOCK
HIGH BIAS ALARM
HIGH TX_P ALARM
LOW TX_P ALARM
SOFT TX-D
VCC2 OR VCC3
P-DOWN/RST
TX-D
FETG
INT
GAIN
ALARM FLAGSW
ARNING FLAGS
MASKING BITS
ADC 13 BIT
OFFSET
RIGHT
SHIFTING
I2C
INTERFACE
MEASURED DATA
COMP
ARA
TORS
VCC3
VCC3
INTERRUPT
MOD-NR
GND
LOWER MEMORY
ADDRESS
R/W
DATA BUS
ADDRESS
R/W
DATA BUS
INT
TABLE-SELECT BYTE
TABLE
01h
SERIAL ID
DATA
TABLE
02h
EEPROM
TABLE
03h
LUT
TABLE
05h
THRSET
TABLE
04h
MODULE
CONFIG
THRSET
MODSET
BIASSET
HIGH BIAS QT
IBMDAEXT(IBMD)
BIAS AND
MODULATION
ENABLE
MASKING BITS
RPU
RPURPU
MISC
CONTROL
SIGNALS
TEMPERATURE
CONTROLLED
WITH
LUT
TEMPERATURE
SENSOR
VCC3
I TO V
DS1862
DS1862
XFP Laser Control and Digital Diagnostic IC
Detailed Description

The DS1862’s block diagram is described in detail
within the following sections and memory map/memory
description.
Automatic Power Control (APC)

The DS1862’s APC is accomplished by closed-loop
adjustment of the bias current (BIASSET) until the feed-
back current (BMD) from a photodiode matches the
value determined by the APC registers. The relation-
ship between the APC register and IBMDis given by:
IBMD= 5.859μA x APCC<7:0> +
(1.464μA x APCF<1:0>)
where APCC<7:0> is the 8-bit value in Table 04h, Byte
84h that controls the coarse BMD current, and
APCF<1:0> is the 2-bit value that controls the fine BMD
current.
The BMD pin appears as a voltage source in series with
two resistors. The overall equivalent resistance of the
BMD input pin can be closely approximated by the plot
in Figure 8. The voltage that appears on the BMD pin,
assuming no external current load, is 1.2V if BMD is in
sink-current mode (SRC_SINK_B = 0) or 2.0V if BMD is
set to source current (SRC_SINK_B = 1). This allows the
photodiode to be referenced to either VCC3or GND.
When the control loop is at steady state, the BMD current
setting matches the current that is measured by the IBMD
voltage across the internal resistance. During a transient
period, the DS1862 adjusts the current drive on the
BIASSET pin to bring the loop into steady state. The
DS1862 is designed to support loop gains of 1/20 to 10.
On power-up, the BMD current ramps up to the previ-
ously saved current setting in EEPROM APC registers.
While operating, the DS1862 monitors the BMD current.
If it begins to deviate from the desired (set) IBMDvalue,
the current on the BIASSET pin is again adjusted to
compensate.
Extinction Ratio Control
Lookup Table (LUT)

The DS1862 uses a temperature indexed lookup table
(LUT) to control the extinction ratio. The MODSET pin is
capable of sinking current based on the 8-bit binary
value that is controlling it. The DS1862 also features a
user-configurable current range to increase extinction
ratio resolution. Five current ranges, as described in
Table 1, are available to control the current entering
MODSET.
IBMD
VOLTAGE
BMD
NOTE: VBMD IS

CONTROLLED BY THE
SRC_SINK_B BIT IN
TABLE 04h.
IBMD (mA)
BMD
BMD RESISTANCE vs. BMD SUPPLY CURRENT

VBMD
RBMD
Figure 8. Approximate Model of the BMD Input
Table 1. Selectable Current Ranges for
MODSET
LUT CURRENT RANGE
TABLE 04h, BYTE 86h<2:0>
CURRENT RANGE
(μA)

000 0 to 75
001 0 to 150
010 0 to 300
011 0 to 600
100 0 to 1200
DS1862
XFP Laser Control and Digital Diagnostic IC

If the largest current range is selected, the maximum
value of FFh (from LUT) corresponds to a 1200μA sink
current. Regardless of the current range, the MODSET
value always consists of 256 steps, including zero.
IMODSETcan be controlled automatically with the tem-
perature-based lookup table, or by three other manual
methods.
Automatic temperature addressed lookup is accom-
plished by an internal or external temperature sensor
controlling an address pointer. This pointer indexes
through 127 previously loaded 8-bit current values
stored in the LUT. Each one of the 127 temperature
slot locations corresponds to a 2°C increment over
the -40°C to +102°C temperature range. Any tempera-
ture above or below these points causes the code in
the first or last temperature slot to be indexed. Both the
internal temperature sensor and an external sensor
connected to AUX2MON are capable of providing a
signal to control the extinction ratio automatically with
an indexed LUT. Table 2 illustrates the relationship
between the temperature and the memory locations in
the LUT.
Automatic and manual control of MODSET is controlled
by two bits, TEN and AEN, that reside in Table 04h,
Byte B2h. By default (from factory) TEN and AEN are
both set, causing complete automatic temperature-
based lookup. If TEN and/or AEN are altered, the
DS1862 is set to one of the manual modes. Table 3
describes manual mode functionality.
Table 2. Temperature Lookup Table
TEMPERATURE (°C)CORRESPONDING LOOKUP
TABLE ADDRESS

< -40 80h
-40 80h
-38 81h
-36 82h
… …
+96 C4h
+98 C5h
+100 C6h
+102 C7h
> +102 C7h
Table 3. Truth Table for TEN and AEN Bits
TENAENDS1862 LUT FUNCTIONALITY

0 0
Manual mode that allows users to write a
value directly to the LUT VALUE register
(Table 04h, Byte B1h) to drive MODSET. While
in this mode, the LUT INDEX POINTER register
is not being updated, and no longer drives the
LUT VALUE register.
0 1
Manual mode that allows users to write a
value directly to the LUT VALUE register
(Table 04h, Byte B1h) to drive MODSET. While
in this mode, the LUT INDEX POINTER register
is still being updated; however, it no longer
drives the LUT VALUE register.
1 0
Manual mode that allows users to write a
value to the LUT INDEX POINTER register
(Table 04h, Byte B0), then the DS1862
updates the LUT VALUE register (Table 04h,
Byte B1h) based on the user’s index pointer.
1 1
Automatic mode (factory default). This mode
automatically indexes the LUT based on
temperature, placing the resulting LUT
address in the LUT INDEX POINTER register
(Table 04h, Byte B0h). Then the MODSET
setting is transferred from that LUT address to
the LUT VALUE register (Table 04h, Byte B1h).
Lastly, the IMODSET is set to the new MODSET
code.
DS1862
XFP Laser Control and Digital Diagnostic IC
Monitor Channels

The DS1862 has seven monitored voltage signals that
are polled in a round-robin multiplexed sequence and
are updated with the frame rate, tFRAME. All channels
are read as 16-bit values, but have 13-bit resolution,
and with the exception of temperature measurements,
all channels are stored as unsigned values. The resulting
16-bit value for all monitored channels, except internal
temperature, is calculated by internally averaging the
analog-to-digital result eight times. The resulting internal
temperature monitor channel is averaged 16 times. See
the Internal Calibrationsection for a complete descrip-
tion of each channel’s method(s) of internal calibration.
The AUX1MON, AUX2MON, and VCC2/3 monitor chan-
nels are optional and can be disabled. This feature
allows for shorter frame rate for the essential monitor
channels. Channels that cannot be disabled are inter-
nal temperature, BMD, RSSI, and IBIASMON. A table of
full-scale (FS) signal values (using factory internal cali-
bration without right shifting) and the resulting FS code
values for all seven channels is provided in Table 4.
Measuring Temperature—Internal or External

The DS1862 is capable of measuring temperature on
three different monitor channels: internal temperature
sensor, AUX1MON, and AUX2MON. Only the internal
temperature and AUX2MON channels are capable of
indexing the LUT to control the extinction ratio. To use
an external temperature sensor on AUX2MON, the
TEMP_INT/EXT bit in Table 04h, Byte 8Bh, must be set.
While AUX2MON controls the extinction ratio, the inter-
nal temperature sensor does not stop running; despite
extinction ratio control by AUX2MON, it is this internal
temperature signal that continues to control the status
of temperature flags. Also, when TEMP_INT/EXT = 1,
the internal temperature clamps at -40°C and
+103.9375°C,and when TEMP_INT/EXT = 0 it clamps at -
120°C and +127.984°C. AUX2MON, however, does have
its own flag to indicate an out-of-tolerance condition and
assert the INTERRUPTpin.
Both AUX1MON and AUX2MON can be used to mea-
sure temperature as a function of voltage on their
respective pins. They can be enabled by selecting
either 0h or 4h from Table 5. Internal (or external) cali-
bration may be required to transmute the input voltage
to the desired two’s-complement digital code, readable
from the result registers in lower memory, Bytes 6Ah,
6Bh, 6Ch, 6Dh.
Measuring VCC2/3

The DS1862 has the flexibility to internally measure
either VCC2or VCC3to monitor supply voltage. VCC2or
VCC3is user selectable by the VCC2/3_SEL bit in Table
01h, Byte DCh. To remove VCC2/3from the round-robin
monitor update scheme, despite having VCC2or VCC3
selected to be monitored, the Reserve_EN bit in Table
04h, Byte 8Bh can be programmed to a 0. The analog
power-on-reset flag, POA, indicates the status of VCC3
power supply. Even though POA seems to behave simi-
larly to VCC2/3monitor channel, it is completely sepa-
rate and has no connection.
Measuring APC and Laser Parameters—BMD,
IBIASMON, RSSI

BMD and BIASSET are used to control and monitor the
laser functionality. Regardless of the set BMD current in
the APC register, the DS1862 measures BMD pin cur-
rent and uses this value not only to adjust the current
on the BIASSET pin, but also to monitor TX-P as well.
The IBIASMON pin is used to input a voltage signal to
the DS1862 that can be used to monitor the bias cur-
rent through the laser. This monitor channel does not
drive the HIGH BIAS quick-trip (QT) alarms for safety
Table 4. Monitor Channel FS and LSB Detail
SIGNAL+FS SIGNAL+FS (hex)-FS SIGNAL-FS (hex)LSB

Temperature 127.984°C 7FF8 -120°C 8800 0.0625°C
VCC2/3 6.5528V FFF8 0V 0000 100μV
IBIASMON 2.4997V FFF8 0V 0000 38.147μV
RSSI 2.4997V FFF8 0V 0000 38.147μV
AUX1MON 6.5528V FFF8 0V 0000 38.147μV
AUX2MON 6.5528V FFF8 0V 0000 38.147μV
BMD (TX-P) 1.5mA FFF8 0mA 0000 22.888nA
RESERVE_EN VCC2/3_SEL RESULT

0 0 VCC2/3 result not enabled.
0 1 VCC2/3 result not enabled.
1 0 VCC3 is being measured.
1 1 VCC2 is being measured.
DS1862
XFP Laser Control and Digital Diagnostic IC

fault functionality, current on the BIASSET pin is moni-
tored by the DS1862 to control the HIGH BIAS quick-
trip alarm. Similar to TX-P, the RSSI pin is used to
measure the received power, RX-P.
Measuring Voltage Quantities
using AUX1MON and AUX2MON

AUX1MON and AUX2MON are auxiliary monitor inputs
that may be used to measure additional parameters.
AUX1/2MON feature a user-selectable register that
determines the measured value’s units (i.e., voltage,
current, or temperature). In addition to indicating units,
some of the 4-bit op codes, in Table 5, also place the
part in special modes used for alarms and faults inter-
nally. Whichever units’ scale is selected, the DS1862 is
only capable of measuring a positive voltage quantity,
therefore internal or external calibration may be
required to get the binary value to match the measured
quantity. A table of acceptable units and/or their corre-
sponding user-programmable 4-bit op code is provid-
ed below.
Alarms and Warning Flags
Based on Monitor Channels

All of the monitor channels feature alarm and warning
flags that are asserted automatically as user-pro-
grammed thresholds are internally compared with mon-
itor channel results. Flags may be set, which, if not
masked, will generate an interrupt on the INTERRUPT
pin or generate a safety fault. Whenever VCC2/3,
AUX2MON, AUX1MON, RSSI, and internal temperature
go beyond their threshold trip points and the corre-
sponding mask bit is 0, an interrupt is generated on the
INTERRUPTpin and a corresponding warning or alarm
flag is set. Similarly, a safety fault occurs whenever
BMD or BIASSET go beyond threshold trip points.
When this happens, the FETG pin immediately asserts
and BIASSET and MODSET currents are shut down.
Monitor Channel Conversion Example

Table 6 provides an example of how a 16-bit ADC code
corresponds to a real life measured voltage using the
factory-set calibration on either RSSI or IBIASMON. By
factory default, the LSB is set to 38.147μV.
To calculate VCC2, VCC3, AUX1MON, or AUX2MON,
convert the unsigned 16-bit value to decimal and multi-
ply by 100μV.
To calculate the temperature (internal), treat the two’s-
complement value binary number as an unsigned
binary number, then convert it to decimal and divide by
256. If the result is grater than or equal to 128, subtract
256 from the result.
Temperature: high byte = -128°C to +127°C signed;
low byte = 1/256°C.
Table 5. AUX1/2MON Functionality
Selection (Unit Selection)
VALUEDESCRIPTION OF AUX1/2MON INTENDED USE
(UNITS OF MEASURE)

0000b Auxiliary monitoring not implemented
0001b APD bias voltage (16-bit value is voltage in units
of 10mV)
0010b Reserved
0011b TEC current (mA) (16-bit value is current in units
of 0.1mA)
0100b Laser temperature (same encoding as module
temperature)
0101b Laser wavelength
0110b +5V supply voltage (encoded as primary voltage
monitor)
0111b +3.3V supply voltage (encoded as primary
voltage monitor)
1000b +1.8V supply voltage (encoded as primary
voltage monitor) (VCC2)
1001b -5.2V supply voltage (encoded as primary voltage
monitor)
1010b +5V supply current (16-bit value is current in
0.1mA)
1101b +3.3V supply current (16-bit value is current in
0.1mA)
1110b +1.8V supply current (16-bit value is current in
0.1mA)
1111b -5.2V supply current (16-bit value is current in
0.1mA)
Table 6. A/D Conversion Example
MSB (BIN)LSB (BIN)VOLTAGE (V)

11000000 00000000 1.875
10000000 10000000 1.255
Table 7. Temperature Bit Weights

S 26 25 24 23 22 21 20
2-1 2-2 2-3 2-4 2-5 — — —
DS1862
XFP Laser Control and Digital Diagnostic IC
Internal Calibration

The DS1862 has two means for scaling an analog input
to a digital result. The two devices alter the gain and
offset of the signal to be calibrated. All of the inputs
except internal temperature have unique registers for
both the gain and the offset that can be found in Table
04h. See the table below for a complete description of
internal calibration capabilities including right-shifting
for all monitor channels.
To scale a specific input’s gain and offset, the relation-
ship between the analog input and the expected digital
result must be known. The input that would produce a
corresponding digital result of all zeroes is the null
value (normally this input is GND). The input that would
produce a corresponding digital result of all ones is the
full-scale (FS) value minus one LSB. The FS value is
also found by multiplying an all ones digital value by
the weighted LSB. For example, a digital reading is 16
bits long, assume that the LSB is known to be 50μV,
then the FS value would be 216x 50μV = 3.2768V.
A binary search can be used to find the appropriate
gain value to achieve the desired FS of the converter.
Once the gain value is determined, then it can be
loaded into the appropriate channels’ Gain register.
This requires forcing two known voltages on to the
monitor input pin. For best results, one of the forced
voltages should be the NULL input and the other
should be 90% of FS. Since the LSB of the least signifi-
cant byte in the digital reading register is known, the
expected digital results are also known for both the null
and FS value inputs. Figure 9 describes the hysteresis
built into the DS1862’s LUT functionality.
With the exception of BMD, which can source or sink
current, all monitored channels are high impedance
and are only capable of directly measuring a voltage. If
other measured quantities are desired, such as light,
frequency, power, current, etc., they must be converted
to a voltage. In this situation the user is not interested in
voltage measurement on the monitored channel, but
the measurement of the desired parameter. Only the
relationship between the indirect measured quantity
(light, frequency, power, current, etc.) to the expected
digital result must be known.
An example of gain scaling using the recommended
binary search procedure is provided with the following
pseudo code.
To help will the computation, two integers need to be
defined: count 1 and count 2. CNT1 = NULL / LSB and
CNT2 = 90%FS / LSB. CLAMP is the largest result that
can be accommodated.
Table 8. Temperature Conversion
Examples
MSB (BIN)LSB (BIN)TEMPERATURE (°C)

01000000 00000000 +64
01000000 00001000 +64.03215
01011111 00000000 +95
11110110 00000000 -10
11011000 00000000 -40
Table 9. Internal Calibration Capabilities
SIGNALINTERNAL
SCALING
INTERNAL
OFFSET
RIGHT-
SHIFTING

Temperature — x —
VCC2/3 x x —
IBIASMON x x x
RSSI (RX-P) x x x
AUX1MON x x x
AUX2MON x x x
BMD (TX-P) x x x 4681012
TEMPERATURE (°C)
MEMORY LOCATION
INCREASING
TEMPERATURE
DECREASING
TEMPERATURE
Figure 9. Lookup Table Hysteresis
DS1862
XFP Laser Control and Digital Diagnostic IC

/* Assume that the Null input is 0.5V. */
/* In addition, the requirement for LSB is 50μV. */
FS = 65536 * 50e-6; /* 3.2768 */
CNT1 = 0.5 / 50e-6;/* 10000 */
CNT2 = 0.90*FS / 50e-6;/* 58982 */
/* Thus the NULL input of 0.5V and the 90% of FS input
is 2.94912V. */
set the trim-offset-register to zero;
set Right-Shift register to zero (Typically zero.
See the Right-Shifting section);
gain_result = 0h;
CLAMP = FFF8h/2^(Right_Shift_Register);
For n = 15 down to 0
begin
gain_result = gain_result + 2^n;
Force the 90% FS input (2.94912V);
Meas2 = read the digital result from the part;
If Meas2 >= CLAMP then
gain_result = gain_result - 2^n;
Else
Force the NULL input (0.5V);
Meas1 = read the digital result from the part;
if (Meas2 - Meas1) > (CNT2 - CNT1) then
gain_result = gain_result - 2^n;
end;
Set the gain register to gain_result;
The gain register is now set and the resolution of the
conversion will best match the expected LSB. The next
step is to calibrate the offset of the DS1862. With the
correct gain value written to the gain register, again
force the NULL input to the monitor pin. Read the digi-
tal result from the part (Meas1). The offset value is
equal to negative value of Meas1.
The calculated offset is now written to the DS1862 and
the gain and offset-scaling procedure is complete.
Right-Shifting A/D Conversion Result
(Scalable Dynamic Ranging)

Right-shifting is a digital method used to regain some
of the lost ADC range of a calibrated system. If right-
shifting is enabled, by simply loading a non-zero value
into the appropriate Right-Shifting Register, then the
DS1862 shifts the calibrated result just before it is
stored into the monitor channels’ register. If a system is
calibrated so the maximum expected input results in a
digital output value of less than 7FFFh (50% of FS),
then it is a candidate for using the right-shifting
method.
If the maximum desired digital output is less than
7FFFh, then the calibrated system is using less than 1/2
the ADC’s range. Similarly, if the maximum desired dig-
ital output is less than 1FFFh, then the calibrated sys-
tem is only using 1/8th the ADC’s range. For example, if
an applied maximum analog signal yields a maximum
digital output less than 1FFCh, then only 1/8th of the
ADC’s range is used. Right-shifting improves the reso-
lution of the measured signal as part of internal calibra-
tion. Without right-shifting, the 3 MS bits of the ADC will
never be used. In this example, a value of 3 for the
right-shifting maximizes the ADC range and a larger
gain setting must be loaded to achieve optimal conver-
sion. No resolution is lost since this is a 13-bit converter
that is left justified. The value can be right-shifted 3
times without losing any resolution. The following table
describes when the right-shifting method can be effec-
tively used.
OFFSETREGISTERMeas_()=−⎡⎢⎤⎥
Table 10. Right-Shifting Selection
OUTPUT RANGE USED WITH
ZERO RIGHT-SHIFTS
NUMBER OF RIGHT-
SHIFTS NEEDED

0h .. FFFFh 0
0h .. 7FFFh 1
0h .. 3FFFh 2
0h .. 1FFFh 3
0h .. 0FFFh 4
DS1862
XFP Laser Control and Digital Diagnostic IC
Warning and Alarm Logic Based on
AUX1/2MON, VCC2/3, Temp, RX-P,
and IBIASMON

The DS1862 is capable of generating an alarm and/or
warning whenever an analog monitored channel goes
out of a user-defined tolerance. Temperature, bias cur-
rent (based on IBIASMON), receive power (based on
RSSI), AUX1MON, AUX2MON, and VCC2/3, are moni-
tored channels that generate latched flags. See the fig-
ure below for more detail pertaining to AUX1MON and
AUX2MON. Flags are latched into a high state the first
time a monitored channel goes out of the defined oper-
ating window and for each monitored signal there is a
Mask bit that can be set to prevent the corresponding
alarm or warning flag from being set. Once a flag is set,
it is cleared by simply reading its memory location.
AUX1/2MON LOGIC

AUX1MON (PIN)
AUX2MON (PIN)
MASK BIT
AUX1MON
AUX2MON
ADC
THRESHOLD
AUX1MON
(APD MODE)LATCHED-APD-
SUPPLY-FAULTAUX2MON
(APD MODE)
INTERRUPT (PIN)
*COMPARATOR LOGIC IS
DUPLICATED FOR HIGH
AND LOW ALARMS AND
WARNINGS.
ADC
THRESHOLD
4-BIT UNIT SELECT
TCH
AUX1MON
(LASER WL MODE)LATCHED-
WAVELENGTH-ULAUX2MON
(LASER WL MODE)
TCH
AUX1MON
(VEE5 MODE)LATCHED-VEE5
AUX2MON
(VEE5 MODE)
TCH
AUX1MON
(VCC2 MODE)LATCHED-VCC2
AUX2MON
(VCC2 MODE)
TCH
AUX1MON
(TEC MODE)LATCHED-TEC-
FAULTAUX2MON
(TEC MODE)
TCH
AUX1MON
(VCC5 MODE)LATCHED-VCC5
AUX2MON
(VCC5 MODE)
TCH
AUX1MON
(VCC3 MODE)LATCHED-VCC3
AUX2MON
(VCC3 MODE)
TCH
ANY FLAG
CORRESPONDING MASK
BIT
Figure 10. AUX1/2MON Monitor Logic
DS1862
XFP Laser Control and Digital Diagnostic IC
Warning and Alarm Logic Based on
Signal Conditioners

The DS1862 also has flags that are set by certain logical
conditions on signal conditioner (SC) pins: SC-RX-LOL,
SC-RX-LOS, SC-TX-LOS. Similarly, for each latched
signal conditioner flag there are also mask bits that are
capable of preventing the alarm or warning flag from
causing an INTERRUPTpin to assert. Again, flags are
cleared automatically whenever their memory address
is read. See Figure 11 for more detail.
Quick-Trip Logic and FETG
Shutdown Functionality

In addition to alarms and warnings, the DS1862 also
has quick-trip (QT) functionality (sometimes referred to
as fast alarms) that is capable of shutting down the
LASER with the FETG pin in conjunction with shutting
down IMODSETand IBIASSET. IBMDand IBIASSETcur-
rents are measured and are compared with user-
defined trip points to set the quick-trip flags: QT LOW
TX-P, QT HIGH TX-P, and QT HIGH BIAS. These flags
are also capable of being masked to prevent FETG
from being asserted when an out-of-tolerance condition
is detected. FETG is not asserted by setting the TX-D
pin, SOFT TX-D, or P-DOWN/RST pin to a high state,
however, IMODSET, and IBIASSETwill shut down. See
Figure 12 for more detail.
SIGNAL CONDITIONER AND MISCELLANEOUS LOGIC

ANY FLAG
ANY MASK BIT
HIGH TX-P
LOW TX-PLATCHED-TX-FAULT
HIGH BIAS
INTERRUPT (PIN)
TIMER
TCH
SC-RX-LOS
(PIN)
LATCHED-RX-NR
SC-RX-LOL
(PIN)
TCH
SC-TX-LOS
(PIN)
LATCHED-TX-NR
LATCHED-TX-FAULT
TCH
P-DOWN/RST
(PIN)LATCHED-RESET-DONE
LATCHED
RX-CDR-NL
TCH
TCHSC-RX-LOL
(PIN)
LATCHED-
RX-LOSRX-LOS (PIN)
TCHSC-RX-LOS
(PIN)
SC-RX-LOL (PIN)
TX-FAULT
LATCHED-
MOD-NR
VCC2-FAULT
*OPEN DRAIN
MOD-NR (PIN)
TCH
Figure 11. Signal Conditioner and Other Logic
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