DS1385-DS1385S-DS1387 Fast Delivery |IC PHOENIX CO.,LIMITED

DS1387 ,RAMified real time clock 4K x 8PIN DESCRIPTION SIGNAL DESCRIPTIONSGND, V – DC power is provided to the device onCCOER – RAM Output ..
DS1388Z-33 ,I2C RTC/Supervisor with Trickle Charger and 512 Bytes EEPROMELECTRICAL CHARACTERISTICS (continued)(V = V to V , T = -40°C to +85°C, unless otherwise noted.) (N ..
DS1388Z-33+ ,I2C RTC/Supervisor with Trickle Charger and 512 Bytes EEPROMFeatures22The DS1388 I C real-time clock (RTC), supervisor, and ♦ Fast (400kHz) I C InterfaceEEPROM ..
DS1388Z-33+ ,I2C RTC/Supervisor with Trickle Charger and 512 Bytes EEPROMApplicationsDS1388Z-33 -40°C to +85°C 8 SO (150 mils) DS138833Portable InstrumentsDS1388Z-5 -40°C t ..
DS1390U-33 ,Low-Voltage SPI/3-Wire RTCs with Trickle ChargerApplications Ordering InformationHand-Held DevicesPIN-PART TEMP RANGE TOP MARKGPS/Telematics Device ..
DS1390U-33 ,Low-Voltage SPI/3-Wire RTCs with Trickle ChargerFeaturesThe low-voltage serial-peripheral interface (SPI™) ♦ Real-Time Clock Counts Hundredths of S ..
DTC143TET1 ,Bias Resistor TransistorELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)ACharacteristic Symbol Min Typ Max Unit ..
DTC143TK , DTA/DTC SERIES
DTC143TM , 100mA / 50V Digital transistors (with built-in resistors)
DTC143TM , 100mA / 50V Digital transistors (with built-in resistors)
DTC143TS , DTA/DTC SERIES
DTC143TS , DTA/DTC SERIES

DS1385-DS1385S-DS1387
RAMified real time clock 4K x 8
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regardingpatents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
DS1385/DS1387
RAMified Real Time Clock 4K x 8
DS1385/DS1387
012496 1/20
FEATURESUpgraded IBM AT computer clock/calendar with
4K x 8 extended RAMTotally nonvolatile with over 10 years of operation in
the absence of powerCounts seconds, minutes, hours, day of the week,
date, month and year with leap year compensationBinary or BCD representations of time, calendar and
alarm12– or 24–hour clock with AM and PM in 12–hour
modeDaylight Savings Time optionMultiplex bus for pin efficiencyInterfaced with software as 64 user RAM locations
plus 4K x 8 of static RAM14–bytes of clock and control registers50–bytes of general purpose RAM4K x 8 SRAM accessible by using separate con-
trol pinsProgrammable square wave output signalBus–compatible interrupt signals (IRQ)Three interrupts are separately software–maskable
and testable:Time–of–day alarm once/second to once/dayPeriodic rates from 122 μs to 500 msEnd–of–clock update cycleAvailable as chip (DS1385 or DS1385S) or stand
alone module with embedded lithium battery and
crystal (DS1387)
ORDERING INFORMATION
DS1385RTC Chip; 24–pin DIP
DS1385SRTC Chip; 28–pin SOIC
DS1387RTC Module; 24–pin DIP
PIN ASSIGNMENT
VCC
SQW
AS0
AS1
IRQ
WER
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
SQW
AS0
AS1
VBAT
IRQ
WER
BGND
ALE
OER
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
DS1387 24–PIN
ENCAPSULATED PACKAGE
(740 MIL FLUSH)
DS1385S 28–PIN SOIC
(330 MIL)
VCC
SQW
AS0
AS1
VBAT
IRQ
WER
GND
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
DS1385 24–PIN DIP
(600 MIL)
DS1385/DS1387
012496 2/20
PIN DESCRIPTION
OER–RAM Output Enable–Crystal Input–Crystal Output
AD0-AD7–Mux’ed Address/Data Bus–RTC Chip Select Input
ALE–RTC Address Strobe–RTC Write Data Strobe–RTC Read Data Strobe
WER–RAM Write Data Strobe
IRQ–Interrupt Request Output (open
drain)
AS1–RAM Upper Address Strobe
AS0–RAM Lower Address Strobe
SQW–Square Wave Output
VCC–+5V Supply
GND–Ground
VBAT–Battery + Supply
BGND–Battery Ground–No Connection
DESCRIPTION
The DS1385/DS1387 RAMified Real Time Clocks
(RTCs) are upward–compatible successors to the in-
dustry standard DS1285/DS1287 RTC’s for PC applica-
tions. In addition to the basic DS1285/DS1287 RTC
functions, 4K bytes of on–chip nonvolatile RAM have
been added.
The RTC functions include a time–of–day clock, a one-
hundred year calendar, time–of–day interrupt, periodic
interrupts, and an end–of–clock update cycle interrupt.
In addition, 50–bytes of user NV RAM are provided with-
in this basic RTC function which can be used to store
configuration data. The clock and user RAM are main-
tained in the absence of system VCC by a lithium battery.
The 4K x 8 additional NV RAM is provided to store a
much larger amount of system configuration data than is
possible within the original 50–byte area. This RAM is
accessed via control signals separate from the RTC,
and is also maintained as nonvolatile storage from the
lithium battery.
OPERATION
The block diagram in Figure 1 shows the pin connec-
tions with the major internal functions of the
DS1385/DS1387. The following paragraphs describe
the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC – DC power is provided to the device on
these pins. VCC is the +5 volt input. When 5 volts are
applied within normal limits, the device is fully accessi-
ble and data can be written and read. When VCC is be-
low 4.25 volts typical, reads and writes are inhibited.
However, the timekeeping function continues unaf-
fected by the lower input voltage. As VCC falls below 3
volts typical, the RAM and timekeeper are switched
over to the energy source connected to the VBAT pin in
the case of the DS1385, or to the internal battery in the
case of the DS1387. The timekeeping function main-
tains an accuracy of ±1 minute per month at 25°C re-
gardless of the voltage input on the VCC pin.
SQW (Square Wave Output) – The SQW pin can output
a signal from one of 13 taps provided by the 15 internal
divider stages of the real time clock. The frequency of the
SQW pin can be changed by programming Register A as
shown in Table 2. The SQW signal can be turned on and
off using the SQWE bit in Register B. The SQW signal is
not available when VCC is less than 4.25 volts typical.
AD0–AD7 (Multiplexed Bi–directional Address/Data
Bus) – Multiplexed buses save pins because address
information and data information time share the same
signal paths. The addresses are present during the first
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the
cycle. Address/data multiplexing does not slow the ac-
cess time of the DS1385/DS1387 since the bus change
from address to data occurs during the internal RAM ac-
cess time. Addresses must be valid prior to the latter
portion of ALE, AS0, or AS1, at which time the
DS1385/DS1387 latches the address from AD0 to AD7.
Valid write data must be present and held stable during
the latter portion of the WR or WER pulses. In a read
cycle, the DS1385/DS1387 outputs eight bits of data
during the latter portion of the RD or OER pulses. The
read cycle is terminated and the bus returns to a high im-
pedance state as RD or OER transitions high.
ALE (RTC Address Strobe Input) – A positive going
address strobe pulse serves to demultiplex the bus.
The falling edge of ALE causes the RTC address to be
latched within the DS1385/DS1387.
RD (RTC Read Input) – RD identifies the time period
when the DS1385/DS1387 drives the bus with RTC
read data. The RD signal is an enable signal for the out-
put buffers of the clock.
DS1385/DS1387
012496 3/20
DS1385/DS1387 BLOCK DIAGRAM Figure 1
ENABLE
VCCSQW
IRQ
DOUBLE
BUFFERED
AD0-AD7
VCC+3V
VBAT
DS1385/DS1387
012496 4/20
WR (RTC Write Input) –The WR signal is an active low
signal. The WR signal defines the time period during
which data is written to the addressed clock register.
CS (RTC Chip Select Input) – The Chip Select signal
must be asserted low during a bus cycle for the RTC
portion of the DS1385/DS1387 to be accessed. CS
must be kept in the active state during RD and WR tim-
ing. Bus cycles which take place without asserting CS
will latch addresses but no access will occur.
IRQ (Interrupt Request Output) – The IRQ pin is an
active low output of the DS1385/DS1387 that can be
tied to an interrupt input on a processor. The IRQ output
remains low as long as the status bit causing the inter-
rupt is present and the corresponding interrupt–enable
bit is set. To clear the IRQ pin, the application program
normally reads the C register.
When no interrupt conditions are present, the IRQ level
is in the high impedance state. Multiple interrupting de-
vices can be connected to an IRQ bus. The IRQ bus is
an open drain output and requires an external pull–up
resistor.
AS0 (RAM Address Strobe Zero) – The rising edge of
AS0 latches the lower eight bits of the 4K x 8 RAM ad-
dress.
AS1 (RAM Address Strobe One) – The rising edge of
AS1 latches the upper four bits of the 4K x 8 RAM ad-
dress.
OER (RAM Output Enable) – OER is active low and
identifies the time period when the DS1385/DS1387
drives the bus with RAM read data.
WER (RAM Write Enable) – WER is an active low sig-
nal and is used to perform writes to the 4K x 8 RAM por-
tion of the DS1385/DS1387.
(DS1385 ONLY)
X1, X2 – Connections for a standard 32.768 KHz quartz
crystal. When ordering, request a load capacitance of 6
pF. The internal oscillator circuitry is designed for opera-
tion with a crystal having a specified load capacitance
(CL) of 6 pF. The crystal is connected directly to the X1
and X2 pins. There is no need for external capacitors or
resistors. Note: X1 and X2 are very high impedance
nodes. It is recommended that they and the crystal be
guard–ringed with ground and that high frequency sig-
nals be kept away from the crystal area. For more
information on crystal selection and crystal layout con-
siderations, please consult Application Note 58, “Crys-
tal Considerations with Dallas Real Time Clocks”.
VBAT, BGND – Battery input for any standard 3 volt lithi-
um cell or other energy source. Battery voltage must be
held between 2.5 and 3.7 volts for proper operation. The
nominal write protect trip point voltage is set by the inter-
nal circuitry and is 4.25 volts typical. A maximum load of
1 μA at 25°C and 3.0V on VBAT should in the absence of
power be used to size the external energy source.
The battery should be connected directly to the VBAT pin.
A diode must not be placed in series with the battery to
the VBAT pin. Furthermore, a diode is not necessary
because reverse charging current protection circuitry is
provided internal to the device and has passed the
requirements of Underwriters Laboratories for UL listing
(E99151).
ADDRESS MAP
The address map of the DS1385/DS1387 is shown in
Figure 2. The address map consists of the RTC and the
4K X 8 NV SRAM section. The RTC section contains
50–bytes of user RAM, 10–bytes of RAM that contain
the RTC time, calendar, and alarm data, and 4–bytes
which are used for control and status. All 64–bytes can
be directly written or read except for the following:Registers C and D are read-only.Bit–7 of Register A is read-only.The high order bit of the seconds byte is read-only.
RTC (REAL TIME CLOCK)
The RTC function is the same as the DS1287 Real Time
Clock. Access to the RTC is accomplished with four
controls: ALE, RD, WR and CS. The RTC is the same in
the DS1287 with the following exceptions:The MOT pin on the DS1285/DS1287 is not present
on the DS1385/DS1387. The bus selection capabili-
ty of the DS1285/DS1287 has been eliminated. Only
the Intel bus interface timing is applicable.The RESET pin on the DS1285/DS1287 is not pres-
ent on the DS1385/DS1387. The DS1385/DS1387
will operate the same as the DS1285/DS1287 with
RESET tied to VCC.
DS1385/DS1387
012496 5/20
ADDRESS MAP DS1385/DS1387 Figure 2
BINAR
OR BCD INPUTS
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by read-
ing the appropriate register bytes shown in Table 1. The
time, calendar and alarm are set or initialized by writing
the appropriate register bytes. The contents of the time,
calendar and alarm registers can be either Binary or
Binary–Coded Decimal (BCD) format. Table 1 shows
the binary and BCD formats of the twelve time, calendar
and alarm locations.
Before writing the internal time, calendar and alarm reg-
isters, the SET bit in Register B should be written to a
logic one to prevent updates from occurring while ac-
cess is being attempted. Also at this time, the data for-
mat (binary or BCD), should be set via the data mode bit
(DM) of Register B. All time, calendar and alarm regis-
ters must use the same data mode. The set bit in Regis-
ter B should be cleared after the data mode bit has been
written to allow the real–time clock to update the time
and calendar bytes.
Once initialized, the real–time clock makes all updates
in the selected mode. The data mode cannot be
changed without reinitializing the ten data bytes. The
24/12 bit cannot be changed without reinitializing the
hour locations. When the 12–hour format is selected,
the high order bit of the hours byte represents PM when
it is a logic one. The time, calendar and alarm bytes are
always accessible because they are double buffered.
Once per second the 10–bytes are advanced by one
second and checked for an alarm condition. If a read of
the time and calendar data occurs during an update, a
problem exists where seconds, minutes, hours, etc.
may not correlate. The probability of reading incorrect
time and calendar data is low. Several methods of
avoiding any possible incorrect time and calendar reads
are covered later in this text.
The three alarm bytes can be used in two ways. First,
when the alarm time is written in the appropriate hours,
minutes and seconds alarm locations, the alarm inter-
rupt is initiated at the specified time each day if the alarm
enable bit is high. The second method is to insert a
“don’t care” state in one or more of the three alarm bytes.
The “don’t care” code is any hexadecimal value from C0
to FF. The two most significant bits of each byte set the
“don’t care” condition when at logic 1. An alarm will be
generated each hour when the “don’t care” bits are set in
the hours byte. Similarly, an alarm is generated every
minute with “don’t care” codes in the hours and minute
alarm bytes. The “don’t care” codes in all three alarm
bytes create an interrupt every second.
DS1385/DS1387
012496 6/20
TIME, CALENDAR AND ALARM DATA MODES Table 1
USER NONVOLATILE RAM – RTC
The 50 user nonvolatile RAM bytes are not dedicated to
any special function within the DS1385/DS1387. They
can be used by the application program as nonvolatile
memory and are fully available during the update cycle.
This memory is directly accessible in the RTC section.
INTERRUPTS
The RTC plus RAM includes three separate, fully auto-
matic sources of interrupt for a processor. The alarm in-
terrupt can be programmed to occur at rates from once
per second to once per day. The periodic interrupt can
be selected for rates from 500 ms to 122 μs. The
update–ended interrupt can be used to indicate to the
program that an update cycle is complete. Each of
these independent interrupt conditions is described in
greater detail in other sections of this text.
The application program can select which interrupts, if
any, are going to be used. Three bits in Register B en-
able the interrupts. Writing a logic 1 to an interrupt–en-
able bit permits that interrupt to be initiated when the
event occurs. A logic 0 in an interrupt–enable bit prohib-
its the IRQ pin from being asserted from that interrupt
condition. If an interrupt flag is already set when an in-
terrupt is enabled, IRQ is immediately set at an active
level, although the interrupt initiating the event may
have occurred much earlier. As a result, there are cases
where the program should clear such earlier initiated in-
terrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde-
pendent of the state of the corresponding enable bit in
Register B. The flag bit can be used in a polling mode
without enabling the corresponding enable bits. When a
flag is set, an indication is given to software that an inter-
rupt event has occurred since the flag bit was last read.
However, care should be taken when using the flag bits
as they are cleared each time Register C is read.
Double latching is included with Register C so that bits
which are set remain stable throughout the read cycle.
All bits which are set (high) are cleared when read and
new interrupts which are pending during the read cycle
are held until after the cycle is completed. One, two or
three bits can be set when reading Register C. Each uti-
lized flag bit should be examined when read to ensure
that no interrupts are lost.
DS1385/DS1387
012496 7/20
The alternative flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQ
pin is asserted low. IRQ is asserted as long as at least
one of the three interrupt sources has its flag and enable
bits both set. The IRQF bit in Register C is a one when-
ever the IRQ pin is being driven low. Determination that
the RTC initiated an interrupt is accomplished by read-
ing Register C. A logic one in bit–7 (IRQF bit) indicates
that one or more interrupts have been initiated. The act
of reading Register C clears all active flag bits and the
IRQF bit.
OSCILLATOR CONTROL BITS
When the DS1385/DS1387 is shipped from the factory,
the internal oscillator is turned off. This feature prevents
the lithium battery from being used until it is installed in a
system. A pattern of 010 in bits 6 through 4 of Register A
will turn the oscillator on and enable the countdown
chain. A pattern of 11X will turn the oscillator on, but
holds the countdown chain of the oscillator in reset. All
other combinations of bits 6 through 4 keep the oscilla-
tor off.
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made available to a
1–of–15 selector, as shown in the block diagram of Fig-
ure 1. The first purpose of selecting a divider tap is to
generate a square wave output signal on the SQW pin.
The RS3–RS0 bits in Register A establish the square
wave output frequency. These frequencies are listed in
Table 2. The SQW frequency selection shares its
1–of–15 selector with the periodic interrupt generator.
Once the frequency is selected, the output of the SQW
pin can be turned on and off under program control with
the square wave enable bit (SQWE).
PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 2
DS1385/DS1387
012496 8/20
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an
active state from once every 500 ms to once every
122 μs. This function is separate from the alarm inter-
rupt which can be output from once per second to once
per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave fre-
quency (see Table 1). Changing the Register A bits af-
fects both the square wave frequency and the periodic
interrupt output. However, each function has a separate
enable bit in Register B. The SQWE bit controls the
square wave output. Similarly, the periodic interrupt is
enabled by the PIE bit in Register B. The periodic inter-
rupt can be used with software counters to measure in-
puts, create output intervals or await the next needed
software function.
UPDATE CYCLE
The DS1385/DS1387 executes an update cycle once
per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user
copy of the double buffered time, calendar and alarm by-
tes is frozen and will not update as the time increments.
However, the time countdown chain continues to update
the internal copy of the buffer. This feature allows time to
maintain accuracy independent of reading or writing the
time, calendar and alarm buffers and also guarantees
that time and calendar information is consistent. The up-
date cycle also compares each alarm byte with the cor-
responding time byte and issues an alarm if a match or if
a “don’t care” code is present in all three positions.
There are three methods that can handle access of the
real–time clock that avoid any possibility of accessing
inconsistent time and calendar data. The first method
uses the update–ended interrupt. If enabled, an inter-
rupt occurs after every up date cycle that indicates that
over 999 ms are available to read valid time and date in-
formation. If this interrupt is used, the IRQF bit in Regis-
ter C should be cleared before leaving the interrupt rou-
tine.
A second method uses the update–in–progress bit
(UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After
the UIP bit goes high, the update transfer occurs 244 μs
later. If a low is read on the UIP bit, the user has at least
244 μs before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244 μs.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in Register
C (see Figure 3). Periodic interrupts that occur at a rate
of greater than tBUC allow valid time and date informa-
tion to be reached at each occurrence of the periodic in-
terrupt. The reads should be complete within
(tPI/2+tBUC) to ensure that data is not read during the up-
date cycle.
UPDATE–ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
UIP BIT IN
REGISTER A
UF BIT IN
REGISTER C
PF BIT IN
REGISTER C
tPI = Periodic interrupt time interval per Table 1.
tBUC = Delay time before update cycle = 244 μs.
tPI/2
tPI
DS1385/DS1387
012496 9/20
REGISTERS
The DS1385/DS1387 has four control registers which
are accessible at all times, even during the update
cycle.
REGISTER A
MSB LSB
UIP – The Update In Progress (UIP) bit is a status flag
that can be monitored. When the UIP bit is a one, the
update transfer will soon occur. When UIP is a zero, the
update transfer will not occur for at least 244 μs. The
time, calendar and alarm information in RAM is fully
available for access when the UIP bit is zero. The UIP
bit is read only. Writing the SET bit in Register B to a one
inhibits any update transfer and clears the UIP status
bit.
DV2, DV1, DV0 – These three bits are used to turn the
oscillator on or off and to reset the countdown chain. A
pattern of 010 is the only combination of bits that will turn
the oscillator on and allow the RTC to keep time. A pat-
tern of 11X will enable the oscillator but holds the count-
down chain in reset. The next update will occur at 500
ms after a pattern of 010 is written to DV2, DV1, and
DV0.
RS3, RS2, RS1, RS0 – These four rate–selection bits
select one of the 13 taps on the 15–stage divider or dis-
able the divider output. The tap selected can be used to
generate an output square wave (SQW pin) and/or a pe-
riodic interrupt. The user can do one of the following:Enable the interrupt with the PIE bit;Enable the SQW output pin with the SQWE bit;Enable both at the same time and the same rate; orEnable neither.
Table 2 lists the periodic interrupt rates and the square
wave frequencies that can be chosen with the RS bits.
REGISTER B
MSB LSB
SET – When the SET bit is a zero, the update transfer
functions normally by advancing the counts once per
second. When the SET bit is written to a one, any update
transfer is inhibited and the program can initialize the
time and calendar bytes without an update occurring in
the midst of initializing. Read cycles can be executed in
a similar manner. SET is a read/write bit that is not modi-
fied by internal functions of the DS1385/DS1387.
PIE – The Periodic Interrupt Enable bit is a read/write bit
which allows the Periodic Interrupt Flag (PF) bit in Reg-
ister C to drive the IRQ pin low. When the PIE bit is set to
one, periodic interrupts are generated by driving the
IRQ pin low at a rate specified by the RS3-RS0 bits of
Register A. A zero in the PIE bit blocks the IRQ output
from being driven by a periodic interrupt, but the Period-
ic Flag (PF) bit is still set at the periodic rate. PIE is not
modified by any internal DS1385/DS1387 functions.
AIE – The Alarm Interrupt Enable (AIE) bit is a read/
write bit which, when set to a one, permits the Alarm
Flag (AF) bit in register C to assert IRQ. An alarm inter-
rupt occurs for each second that the three time bytes
equal the three alarm bytes including a don’t care alarm
code of binary 11XXXXXX. When the AIE bit is set to
zero, the AF bit does not initiate the IRQ signal. The in-
ternal functions of the DS1385/DS1387 do not affect the
AIE bit.
UIE – The Update Ended Interrupt Enable (UIE) bit is a
read/write bit that enables the Update End Flag (UF) bit
in Register C to assert IRQ. The SET bit going high
clears the UIE bit.
SQWE – When the Square Wave Enable (SQWE) bit is
set to a one, a square wave signal at the frequency set
by the rate–selection bits RS3 through RS0 is driven out
on a SQW pin. When the SQWE bit is set to zero, the
SQW pin is held low. SQWE is a read/write bit.
DM – The Data Mode (DM) bit indicates whether time
and calendar information is in binary or BCD format.
The DM bit is set by the program to the appropriate for-
mat and can be read as required. This bit is not modified
by internal functions. A one in DM signifies binary data
while a zero in DM specifies Binary Coded Decimal
(BCD) data.
24/12 – The 24/12 control bit establishes the format of
the hours byte. A one indicates the 24–hour mode and a
zero indicates the 12–hour mode. This bit is read/write.
DSE – The Daylight Savings Enable (DSE) bit is a read/
write bit which enables two special updates when DSE
is set to one. On the first Sunday in April the time incre-
ments from 1:59:59 AM to 3:00:00 AM. On the last
Sunday in October when the time first reaches 1:59:59
DS1385/DS1387
012496 10/20
AM it changes to 1:00:00 AM. These special updates do
not occur when the DSE bit is a zero. This bit is not af-
fected by internal functions.
REGISTER C
MSB LSB
IRQF - The Interrupt Request Flag (IRQF) bit is set to a
one when one or more of the following are true:
PF = PIE = 1 AF = AIE = 1
UF = UIE = 1
i.e., IRQF = (PF • PIE) + (AF • AIE) + (UF • UIE)
Any time the IRQF bit is a one, the IRQ pin is driven low.
All flag bits are cleared after Register C is read by the
program.
PF – The Periodic Interrupt Flag (PF) is a read–only bit
which is set to a one when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0
bits establish the periodic rate. PF is set to a one inde-
pendent of the state of the PIE bit. When both PF and
PIE are ones, the IRQ signal is active and will set the
IRQF bit. The PF bit is cleared by a software read of
Register C.
AF – A one in the Alarm Interrupt Flag (AF) bit indicates
that the current time has matched the alarm time. If the
AIE bit is also a one, the IRQ pin will go low and a one will
appear in the IRQF bit. A read of Register C will clear
AF.
UF – The Update Ended Interrupt Flag (UF) bit is set af-
ter each update cycle. When the UIE bit is set to one, the
one in UF causes the IRQF bit to be a one which will as-
sert the IRQ pin. UF is cleared by reading Register C.
BIT 3 THROUGH BIT 0 – These are reserved bits of the
status Register C. These bits always read zero and can-
not be written.
REGISTER D
MSB LSB
VRT – The Valid RAM and Time (VRT) bit is set to the
one state by Dallas Semiconductor Corporation prior to
shipment. This bit is not writable and should always be a
one when read. If a zero is ever present, an exhausted
internal lithium energy source is indicated and both the
contents of the RTC data and RAM data are question-
able.
BIT 6 THROUGH BIT 0 – The remaining bits of Register
D are reserved and not usable. They cannot be written
and, when read, they will always read zero.
4K X 8 RAM
The DS1385/DS1387 provides 4K x 8 of on–chip SRAM
which is controlled as nonvolatile storage sustained
from a lithium battery. On power–up, the RAM is taken
out of write–protect status by the internal power OK sig-
nal (POK) generated from the write protect circuitry.
The POK signal becomes active at 4.25 volts (typical).
The on–chip 4K x 8 nonvolatile SRAM is accessed via
the eight multiplexed address/data lines AD7–AD0. Ac-
cess to the SRAM is controlled by three on–chip latch
registers. Two registers are used to hold the SRAM ad-
dress and the third register is used to hold read/write
data. The SRAM address space is from 000H to FFFH.
Four control signals, AS0, AS1, OER, and WER, are
used to access the 4K x 8 SRAM. The address latches
are loaded from the address/data bus in response to ris-
ing edge signals applied to the Address Strobe 0 (AS0)
and Address Strobe 1 (AS1) signals. AS0 is used to
latch the lower 8–bits of address, and AS1 is used to
latch the upper 4–bits of address. It is necessary to
meet the setup and hold times given in the Electrical
Specifications with valid address information in order to
properly latch the address. If the upper or lower order
address is correct from a prior cycle, it is not necessary
to repeat the address latching sequence.
A write operation requires valid data to be placed on the
bus (AD7–AD0) followed by the activation of the Write
Enable RAM (WER) line. Data on the bus will be written
to the RAM provided that the write timing specifications
are met. During a read cycle, the Output Enable RAM
(OER) signal is driven active. Data from the RAM will
become valid on the bus provided that the RAM read ac-
cess timing specifications are met. The WER and OER
signals should never be active at the same time. In addi-
tion, access to the clock/calendar registers and user
RAM (via CS) must not be attempted when the 4K x 8
RAM is being accessed. The RAM is enabled when ei-
ther WER or OER is active. CS is only used for the ac-
cess of the clock calendar registers (including the ex-
tended Dallas registers) and the 50–bytes of user RAM.

Partno	Mfg	Dc	Qty	Available	Descript
DS1385	DALLAS	N/a	4	avai	RAMified real time clock 4K x 8
DS1385S	DALLAS	N/a	35	avai	RAMified real time clock 4K x 8
DS1387		N/a	109	avai	RAMified real time clock 4K x 8