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DS1302-DS1302/
Trickle Charge Timekeeping Chip
FEATURESReal-time clock (RTC) counts seconds,
minutes hours, date of the month, month, day
of the week, and year with leap-year
compensation valid up to 210031-byte, battery-backed, nonvolatile (NV)
RAM for data storageSerial I/O for minimum pin count2.0V to 5.5V full operationUses less than 300nA at 2.0VBurst mode for reading/writing successive
addresses in clock/RAM8-pin DIP or optional 8-pin SOICs for surface
mountSimple 3-wire interfaceTTL-compatible (VCC = 5V)Optional industrial temperature range:
-40°C to +85°CDS1202 compatibleUnderwriters Laboratory (UL) recognized
ORDERING INFORMATIONDS1302 8-Pin DIP (300-mil)
DS1302N8-Pin DIP (Industrial)
DS1302S 8-Pin SOIC (200-mil)
DS1302SN 8-Pin SOIC (Industrial)DS1302Z 8-Pin SOIC (150-mil)
DS1302ZN 8-Pin SOIC (Industrial)
DS1302S-1616-Pin SOIC (300-mil)
DS1302SN-1616-Pin SOIC (Industrial)
PIN ASSIGNMENT
PIN DESCRIPTIONX1, X2 - 32.768kHz Crystal Pins
GND - Ground
RST - Reset
I/O - Data Input/OutputSCLK - Serial Clock
VCC1, VCC2 - Power Supply Pins
DESCRIPTIONThe DS1302 Trickle Charge Timekeeping Chip contains an RTC/calendar and 31 bytes of static RAM. It
communicates with a microprocessor via a simple serial interface. The RTC/calendar provides seconds,
minutes, hours, day, date, month, and year information. The end of the month date is automatically
adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in
DS1302
Trickle Charge Timekeeping ChipVCC2
GND
DS1302 8-Pin DIP (300-mil)
VCC2
GND
DS1302 8-Pin SOIC (200-mil)
DS1302 8-Pin SOIC (150-mil)
DS1302 16-Pin SOIC (300-mil)
VCC1
RST
VCC2
GND
DS1302
Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication.
Only three wires are required to communicate with the clock/RAM: 1) RST(reset), 2) I/O (data line), and
3) SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst
of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock
information on less than 1 microwatt.
The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the
DS1202, the DS1302 has the additional features of dual-power pins for primary and back-up power
supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory.
DS1302
OPERATIONThe main elements of the serial timekeeper (i.e., shift register, control logic, oscillator, RTC, and RAM)
are shown in Figure 1.
DS1302 BLOCK DIAGRAM Figure 1
SIGNAL DESCRIPTIONS
VCC1 – VCC1 provides low-power operation in single supply and battery-operated systems as well as low-power battery backup. In systems using the trickle charger, the rechargeable energy source is connected
to this pin. UL recognized to ensure against reverse charging current when used in conjunction with a
lithium battery.
See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm.
VCC2 – VCC2 is the primary power supply pin in a dual-supply configuration. VCC1 is connected to abackup source to maintain the time and date in the absence of primary power.
The DS1302 will operate from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2
will power the DS1302. When VCC2 is less than VCC1, VCC1 will power the DS1302.
SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface. Thispin has a 40kΩ internal pull-down resistor.
I/O (Data Input/Output) – The I/O pin is the bi-directional data pin for the 3-wire interface. This pin hasa 40kΩ internal pull-down resistor.
RST (Reset) – The reset signal must be asserted high during a read or a write. This pin has a 40kΩinternal pull-down resistor.
X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator is designed for
DS1302
with Dallas Real-Time Clocks.” The DS1302 can also be driven by an external 32.768kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
CLOCK ACCURACYThe accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capactive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. See Application Note58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
COMMAND BYTEThe command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB(Bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar
data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or
output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic
1. The command byte is always input starting with the LSB (bit 0).
ADDRESS/COMMAND BYTE Figure 2
RESET AND CLOCK CONTROLAll data transfers are initiated by driving the RST input high. The RST input serves two functions. First,
RST turns on the control logic, which allows access to the shift register for the address/command
sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte
data transfer.
A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be
valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the RSTinput is low all data transfer terminates and the I/O pin goes to a high impedance state. Data transfer is
illustrated in Figure 3. At power-up, RST must be a logic 0 until VCC > 2.0V. Also SCLK must be at a
DS1302
DATA INPUTFollowing the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge
of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur.
Data is input starting with bit 0.
DATA OUTPUTFollowing the eight SCLK cycles that input a read command byte, a data byte is output on the falling
edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first fallingedge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes
should they inadvertently occur so long as RST remains high. This operation permits continuous burst
mode read capability. Also, the I/O pin is tri-stated upon each rising edge of SCLK. Data is output
starting with bit 0.
BURST MODEBurst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31
decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0
specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar
Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for
the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all
31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless ofwhether all 31 bytes are written or not.
CLOCK/CALENDARThe clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the
clock/ calendar registers is in binary coded decimal format (BCD).
CLOCK HALT FLAGBit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock
oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less
than 100 nanoamps. When this bit is written to logic 0, the clock will start. The initial power on state isnot defined.
AM-PM/12-24 MODEBit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,bit 5 is the second 10-hour bit (20–23 hours).
WRITE PROTECT BITBit 7 of the control register is the write-protect bit. The first seven bits (bits 0–6) are forced to 0 and will
always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high,the write protect bit prevents a write operation to any other register. The initial power on state is not
defined. Therefore the WP bit should be cleared before attempting to write to the device.
TRICKLE CHARGE REGISTERThis register controls the trickle charge characteristics of the DS1302. The simplified schematic of
DS1302
DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2–3) select whether
one diode or two diodes are connected between VCC2 and VCC1. If DS is 01, one diode is selected or if DS
is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS.
The RS bits (bits 0–1) select the resistor that is connected between VCC2 and VCC1. The resistor selectedby the resistor select (RS) bits is as follows:
If RS is 00, the trickle charger is disabled independently of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5V is applied to VCC2 and a super cap isconnected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1
between VCC2 and VCC1. The maximum current IMAX would, therefore, be calculated as follows:
IMAX = (5.0V - diode drop)/R1 � (5.0V - 0.7V) / 2kΩ � 2.2mA
As the super cap charges, the voltage drop between VCC1 and VCC2 will decrease and, therefore, the
charge current will decrease.
CLOCK/CALENDAR BURST MODEThe clock/calendar command byte specifies burst mode operation. In this mode the first eightclock/calendar registers can be consecutively read or written (See Figure 4) starting with bit 0 of address
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer
will occur to any of the eight clock/calendar registers (this includes the control register). The trickle
charger is not accessible in burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The
time information is read from these secondary registers, while the clock may continue to run. This
eliminates the need to re-read the registers in case of an update of the main registers during a read.
RAMThe static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.
RAM BURST MODEThe RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be
consecutively read or written (See Figure 4) starting with bit 0 of address 0.
REGISTER SUMMARYA register data format summary is shown in Figure 4.
DS1302
DATA TRANSFER SUMMARY Figure 3
SINGLE BYTE READ
SINGLE BYTE WRITEIn burst mode, RST is kept high and additional SCLK cycles are sent until the end of the burst.
DS1302
REGISTER ADDRESS/DEFINITION Figure 4
