DS1258AB-70 ,128k x 16 Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10-Year Minimum Data Retention in the CEU V 1 40 CCAbsence of Externa ..
DS1258Y-100# ,128k x 16 Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10-Year Minimum Data Retention in the CEU V 1 40 CCAbsence of Externa ..
DS1259 ,Battery Manager ChipPIN DESCRIPTION2 15VBAT VCCINC - No Connect3 14 NCBFV - Battery Input ConnectionBAT4 13 VCCONCBF - ..
DS1259. ,Battery Manager ChipFEATURES PIN ASSIGNMENT Facilitates uninterruptible power Uses battery only when primary V is not ..
DS1259S ,Battery Manager ChipPIN DESCRIPTION2 15VBAT VCCINC - No Connect3 14 NCBFV - Battery Input ConnectionBAT4 13 VCCONCBF - ..
DS125MB203SQE/NOPB ,12.5Gbps Dual Port MUX and Fanout Buffer 54-WQFN -40 to 85Block Diagram(1)Device InformationMB203PART NUMBER PACKAGE BODY SIZE (NOM)S_INA+S_INA-DS125MB203 WQ ..
DTC114EKA T146 , NPN 100mA 50V Digital Transistors
DTC114EKA T146 , NPN 100mA 50V Digital Transistors
DTC114EKAT146 , NPN 100mA 50V Digital Transistors
DTC114EKAT146 , NPN 100mA 50V Digital Transistors
DTC114EKA-T146 , NPN 100mA 50V Digital Transistors
DTC114EM , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DS1258AB-100-DS1258AB-70
128k x 16 Nonvolatile SRAM
FEATURES ��10-Year Minimum Data Retention in the
Absence of External Power
��Data is Automatically Protected During a
Power Loss
��Separate Upper Byte and Lower Byte Chip-Select Inputs
��Unlimited Write Cycles
��Low-Power CMOS
��Read and Write Access Times as Fast as 70ns
��Lithium Energy Source is Electrically Disconnected to Retain Freshness Until
Power is Applied for the First Time
��Full �10% Operating Range (DS1258Y)
��Optional �5% Operating Range (DS1258AB)
��Optional Industrial Temperature Range of
-40�C to +85�C, Designated IND
PIN ASSIGNMENT PIN DESCRIPTION A0 to A16 - Address Inputs
DQ0 to DQ15 - Data In/Data Out
CEU - Chip Enable Upper Byte
CEL - Chip Enable Lower Byte - Write Enable - Output Enable
VCC - Power (+5V)
GND - Ground
DESCRIPTION The DS1258 128k x 16 nonvolatile (NV) SRAMs are 2,097,152-bit fully static, NV SRAMs, organized as
131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1258 devices can be used in place of solutions that build NV
128k x 16 memory by utilizing a variety of discrete components. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
DS1258Y/AB
128k x 16 Nonvolatile SRAM40-Pin Encapsulated Package
740mil Extended
DQ15
DQ13
DQ11
DQ10
DQ9
DQ8
GND
DQ7
DQ5
DQ6
VCC
WE
GND
CEL
DQ14
DQ12
CEU
DQ4
DQ3DQ1
DQ2
DQ0
DS1258Y/AB
READ MODE The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both
of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is
accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If
CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is
inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU
and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to
the 16 data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CEU, CEL and OE access times are also satisfied. If CEU, CEL, and OE access times are not
satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is
either tCO for CEU, CEL, or tOE for OE rather than address access.
WRITE MODE The DS1258 devices execute a write cycle whenever WE and either/both of CEU or CEL are active (low)
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines
which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or
part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of
the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the
addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word
is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL, or WE. All
address inputs must be kept valid throughout the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled CEU and/or CEL, and OE active) then WE will disable the outputs in tODW from its falling edge.
READ/WRITE FUNCTION Table 1 Read Cycle
Write Cycle
DATA RETENTION MODE The DS1258AB provides full functional capability for VCC greater than 4.75V, and write protects by
4.5V. The DS1258Y provides full functional capability for VCC greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The NV static
DS1258Y/AB
retain data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 4.75V for the DS1258AB and 4.5V for the DS1258Y.
FRESHNESS SEAL The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the
lithium energy source is enabled for battery backup operation.
ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range 0°C to +70°C, -40�C to +85�C for Industrial Parts
Storage Temperature Range -40°C to +70°C, -40�C to +85�C for Industrial Parts
Soldering Temperature See IPC/JEDEC J-STD-020A Specification * This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
DC ELECTRICAL (VCC = 5V ��5% for DS1258AB)
CHARACTERISTICS (tA: See Note 10) (VCC = 5V ��10% for DS1258Y)
DS1258Y/AB
CAPACITANCE (tA = +25�C)
AC ELECTRICAL (VCC = 5V ��5% for DS1258AB)
CHARACTERISTICS (tA: See Note 10) (VCC = 5V ��10% for DS1258Y)
READ CYCLE
DS1258Y/AB
WRITE CYCLE 1 SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
DS1258Y/AB
POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING (tA: See Note 10)
(tA =+25�C)
WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES: 1) WE is high for a Read Cycle. 2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3) tWP is specified as the logical AND of CEU or CEL and WE. tWP is measured from the latter of CEU,
CEL or WE going low to the earlier of CEU, CEL or WE going high. 4) tDS is measured from the earlier of CEU or CEL or WE going high. 5) These parameters are sampled with a 5pF load and are not 100% tested. 6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in
the output buffers remain in a high impedance state during this period.
