DS1249AB-100IND ,100 ns, Vcc=5V+/-5%, 2048 K nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the NC 1 32 V CCabsence of externa ..
DS1249AB-70 ,70 ns, Vcc=5V+/-5%, 2048 K nonvolatile SRAM DS1249Y/AB 2048k Nonvolatile SRAM
DS1249AB-70IND ,2048k Nonvolatile SRAMPIN DESCRIPTION A0 - A17 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE ..
DS1249AB-70IND ,2048k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the NC 1 32 V CCabsence of externa ..
DS1249W-100 ,3.3V 2048k Nonvolatile SRAMPIN DESCRIPTIONA0–A17 - Address InputsDQ0–DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1249Y ,2048k Nonvolatile SRAMPIN DESCRIPTION A0 - A17 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE ..
DTB123YS , Digital transistors (built-in resistors)
DTB123YU , PNP -500mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
DTB133HK , Digital transistors (built-in resistors)
DTB133HS , Digital transistors (built-in resistors)
DTB143EC ,Tech Electronics LTD - Digital transistors (built-in resistors)
DTB143EK ,Tech Electronics LTD - Digital transistors (built-in resistors)
DS1249AB-100IND-DS1249AB-70-DS1249Y-100-DS1249Y-100IND-DS1249Y-70
100 ns, Vcc=5V+/-5%, 2048 K nonvolatile SRAM
FEATURES ��10 years minimum data retention in the
absence of external power
��Data is automatically protected during power
loss
��Unlimited write cycles
��Low-power CMOS operation
��Read and write access times as fast as 70 ns
��Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
��Full ±=10% VCC operating range (DS1249Y)
��Optional ±=5% VCC operating range
(DS1249AB)
��Optional industrial temperature range of
-40°C to +85°C, designated IND
��JEDEC standard 32-pin DIP package
PIN ASSIGNMENT
PIN DESCRIPTION A0 - A17 - Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+5V) GND - Ground
NC - No Connect
DESCRIPTION The DS1249 2048k Nonvolatile SRAMs are 2,097,152-bit, fully static, nonvolatile SRAMs organized as
262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1249Y/AB
2048k Nonvolatile SRAM32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
DQ1
DQ0
VCC
WE
OE
CE
DQ7
DQ5
DQ6
A16
A12
DQ2
GND
DQ4
DQ3
DS1249Y/AB
READ MODE The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs (A0 - A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either tCO for or tOE for OE rather than tACC.
WRITE MODE The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The DS1249AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1249Y provides full-functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protects themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1249AB and 4.5 volts for the
DS1249Y.
FRESHNESS SEAL Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
DS1249Y/AB
ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
DC ELECTRICAL (VCC=5V ±=5% for DS1249AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1249Y)
CAPACITANCE (tA=25°C) DS1249Y/AB
AC ELECTRICAL (VCC=5V ±=5% for DS1249AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1249Y) DS1249Y/AB
READ CYCLE SEE NOTE 1
WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1249Y/AB
WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION SEE NOTE 11
