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DS1235YN/a11avai256K Nonvolatille SRAM


DS1235Y ,256K Nonvolatille SRAMFEATURES 0 Data retention in the absence of Vcc . Data Is automatically protected during power ..
DS1236 ,MicroManager ChipapplicationsRC - Reset Control Standard 16-pin DIP or space-saving 16-pinIN - Early Warning InputS ..
DS1236-10 ,MicroManager ChipFEATURES PIN ASSIGNMENT Holds microprocessor in check during powerVBAT 1 16 RSTtransients Halts a ..
DS1236-10 ,MicroManager Chipapplications.CCO CCV +5V primary power input.CCPF Power-fail indicator, active high, used for exter ..
DS1236-5 ,MicroManager ChipPIN DESCRIPTION Accurate 10% power supply monitoringV - +3-Volt Battery InputBAT Optional 5% powe ..
DS1236AS-10 ,MicroManager Chipapplications.CCO CCV +5V primary power input.CCPF Power-fail indicator, active high, used for exter ..
DTA144GKA , Digital transistors (built-in resistor)
DTA144GKA , Digital transistors (built-in resistor)
DTA144GUA , Digital transistors (built-in resistor)
DTA144TE , -100mA / -50V Digital transistors (with built-in resistor)
DTA144TM , -100mA / -50V Digital transistors (with built-in resistor)
DTA144TT1 ,Bias Resistor Transistor2P POWER DISSIPATION (mW)D,DTA144TT1INFORMATION FOR USING THE SC–59 SURFACE MOUNT PACKAGEMINIMUM RE ..


DS1235Y
256K Nonvolatille SRAM
. Available in 100, 120, 150, and 200 ns read
access tlmes
. Read cycle time equals write cycle time
0 Lithium energy source is electrically discon-
nected to retain freshneSS untll power ls ap-
plled for the first time
. Full & 10% operating range (DS1235Y)
q Optional d: 5% operation range (DS1235AB)
DESCRIPTION
The DS1235Y/AB 256K Nonvolatlle SRAM is a
262, 144-b I t, fully static SRAM organized as
32,768 words by 8 bits. The nonvolatile memory
has a self-contained llthlum energy source and
control circuitry that constantly monitors Vector
an out-ot-tolerance condition. When such a
condition occurs, the lithium energy source ls
automatically switched on and write protection is
uncondltlonally enabled to prevent garbled data.
DALLAS SEMICONDUCTOR CORP 39E 1) EELHLBU UDUBHLB s EDAL
DS!235YIAB
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meme DS1235WAB
samconnuc'ron 256K Nonvolatile SRAM
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FEATURES PIN DESCRIPTION
. Data retention In the absence of Vcc A14 1 Vcc
. Data Is automatically protected during power A: g :1
loss M 4 A8
. Directly replaces 82K x 8 volatile static RAMs fl z 'd,
or EEPROMs
M 7 OEI
. Unlimited write cycles A2 8 AIO
A1 CE\
q Low-power CMOS M Dtt7
000 me
. Over 5 years of data retention Dt21 DQ5
002 004 V
q Standard 28-pin JEDEC pinout GND 003
28-PIN ENCAPSULATED PACKAGE
(720 IM Extended)
PIN NAMES ( l Denotes Condition Low)
A0 - A14 - Address Inputs
CEI - Chip Enable
GND .. Ground
DQO-DQ - Data In/Data Out
Va, - Power (+5V)
WEN - Write Enable
OE) - Output Enable
The nonvolatile SRAM can be used In place of
existlng 32K x 8 SRAMs directly conforming to
the popular bytewlde 28256 EEPROM, allowing
dlrect substitution while enhancing perform-
ance. There Is no limit on the number of write
cyctes that can be executed and no additional
support circuitry is required for microprocessor
Interface.
070290 1/7
DALLAS SEMICONDUCTOR CORP ME I) BELLILBU UDDBHLB 7 EDAL
DS1235WM
READ MODE
The DS1235Y/AB executes a read cycle when-
ever WEN (Write Enable) ls inactive (high) and
CE\ (Chlp Enable) ls active (low). The unlqua
address specified by the 15 address Inputs (A,,-
A, J detlnes which of the 32,768 bytes of data Is
to be accessed. Valid data wlll be available to
the elght data output drivers within tm (Access
Time) after the last address Input slgnal Is
stable, providing that CE\ and OEN (Output
Enable) access tlmes are also satistlad. If om
and CEN access times am not satlsfksd, then
data access must be measured from the later
occurring slgnal (CE\ or OES) and the limiting
parameter is elther tco for CE\ or toi, for OEI,
rather than address access.
WRITE MODE
The DS1235Y/AB is In the write mode whenever
the WEI and CE\ signals are In the active (low)
state after address Inputs are stable. The latter
occurring taltlng edge of CEI or WEN will deter-
mlne the start of the write cycle. The write cycle
is terminated by the earlier rlslng edge of CEI or
WEN. All address Inputs must be kept valid
throughout the wrlte cycle. WEN must return to
the hlgh state fora minimum recoverytime (U)
before another cycle can be initiated. The OEI
control signal should be kept inactive (high)
during write cycles to avoid bus contention.
However, If the output bus has been enabled
(CE\ and OEI active) then WEI will disable the
outputs in tow, from Its talllng edge.
DATA RETENTION MODE
The nonvolatile SRAM provides full functional
capabllity toerc greaterthan 4.5 volts and wrlte
protects by 4.25V nominal (Vcc greater than
4.75V and write protect at 4.62V nominal tor
~081235AB). Data is maintained in the absence
ot Vcc without any additional support circuitry.
The D81235Y/AB constantly monitors V00.
Should the supply voltage decay. the RAM will
automatically write protect itself; all inputs to the
RAM become "don't care" and all outputs are
high Impedance, As Va, falls below approxl-
mately 3.0 volts, the power switching circult
connects the lithium energy source to RAM to
T" trt,-Q3-20
retaln data. During power-up, when Vcc rises
above approximately 3.0 volts, the power
swltchlng clrcult connects external Vcc to the
RAM and disconnects the lithium energy source.
Normal RAM operation can resume after Vco
exceeds 4.5 volts (4.75 voltstorthe DS1235AB),
FRESHNESS SEAL AND SHIPPING
The DSt235Y/AB is shipped from Dallas Semi..
conductorwith the lithium energy source discon-
nected. guaranteeing full energy capacity.
When Va, is first applied at a level of greaterthan
VTP, the llthlum energy source is enabled for
battery backup operatlon.
BATTERY REDUNDANCY -
Battery redundancy ensures reliability. The
DS1235Y/AB contains two lithium energy cells
separated by an Internal Isolation switch. During
battery backup time the cell with the highest
voltage is selected tor use. If one battery fails,
the other battery automatically takes over, The
switch between batteries is transparent to the
070290 2/7
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