DS1216F ,Smart watch ROMFEATURES The DS1216 SmartWatch RAM and SmartWatch Keeps Track of Hundredths of Seconds, ROM socke ..
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DS1216F-DS1216H
Smart watch ROM
GENERAL DESCRIPTION The DS1216 SmartWatch RAM and SmartWatch
ROM sockets are 600-mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM
controller circuit, and an embedded lithium energy
source. The sockets provide an NV RAM solution
for memory sized from 2k x 8 to 512k x 8 with
package sizes from 26 pins to 32 pins. When a
socket is mated with a CMOS SRAM, it provides a
complete solution to problems associated with
memory volatility and uses a common energy
source to maintain time and date. The SmartWatch
ROM sockets use the embedded lithium source to
maintain the time and date only. A key feature of
the SmartWatch is that the watch function remains
transparent to the RAM. The SmartWatch monitors
VCC for an out-of-tolerance condition. When such a
condition occurs, an internal lithium energy source
is automatically switched on and write protection
is unconditionally enabled to prevent loss of watch
and RAM data.
TYPICAL OPERATING CIRCUIT
FEATURES ��Keeps Track of Hundredths of Seconds,
Seconds, Minutes, Hours, Days, Date of the
Month, Months, and Years
��Converts Standard 2k x 8 Up to 512k x 8
CMOS Static RAMs into Nonvolatile Memory
��Embedded Lithium Energy Cell Maintains
Watch Information and Retains RAM Data
��Watch Function is Transparent to RAM
Operation
��Month and Year Determine the Number of
Days in Each Month; Leap-Year
Compensation Valid Up to 2100
��Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power
is Applied for the First Time
��Proven Gas-Tight Socket Contacts
��Full �10% Operating Range
��Operating Temperature Range: 0�C to +70°C
��Accuracy Better Than �1 Minute/Month
at +25�C
ORDERING INFORMATION (See Figure 2 for letter suffix marking identification.)
Selector Guide appears on page 2.
DS1216SmartWatch RAM (DS1216B/C/D/H);
SmartWatch ROM (DS1216E/F)
DS1216 SmartWatch RAM/SmartWatch ROM
PIN DESCRIPTION RST - Reset, Active Low
DQ0 - Data Input/Output 0 (RAM)
A2 - Address Bit 2 (Read/Write [ROM])
A0 - Address Bit 0 (Data Input [ROM])
GND - Ground
CE - Conditioned Chip Enable, Active Low
OE - Output Enable, Active Low
WE - Write Enable, Active Low
VCC - Switched VCC for 28-/32-Pin RAM
VCCB - Switched VCC for 24-Pin RAM
VCCD - Switched VCC for 28-Pin RAM
PIN CONFIGURATIONS SELECTOR GUIDE DS1216 SmartWatch RAM/SmartWatch ROM
DETAILED DESCRIPTION The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600-mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source.
The sockets provide an NV RAM solution for memory sized from 2k x 8 to 512k x 8 with package sizes
from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to
problems associated with memory volatility and uses a common energy source to maintain time and date.
The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A
key feature of the SmartWatch is that the watch function remains transparent to the RAM. The
SmartWatch monitors VCC for an out-of-tolerance condition. When such a condition occurs, an internal
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent loss of watch and RAM data.
Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM
take up no more area than the memory alone. The SmartWatch uses the VCC, data I/O 0, CE, OE, and WE
for RAM and watch control. All other pins are passed straight through to the socket receptacle.
The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, date, months, and years. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either
24-hour or 12-hour format with an AM/PM indicator.
OPERATION Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of
64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and
either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is
disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC
registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC
registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low
during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match
sequence.
PATTERN MATCH—RAM Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control
of chip enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory
location using the CE and OE control of the SmartWatch starts the pattern recognition sequence by
moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,
the write cycles generated to gain access to the SmartWatch are also writing data to a location in the
mated RAM. The preferred way to manage this requirement is to set aside just one address location in
RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the
DS1216 SmartWatch RAM/SmartWatch ROM
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for 64 write cycles as described above until all the bits in the comparison register have been matched (this
bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data
transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch
to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to
other locations outside the memory block can be interleaved with CE cycles without interrupting the
pattern recognition sequence or data transfer sequence to the SmartWatch.
PATTERN MATCH—ROM Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits
that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the
proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior
to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read
cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition
starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of
the 64-bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above, until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is
enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause
the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on
the level of /WRITE READ (A2).
After power-up, the controller could be in the 64-bit clock register read/write sequence (from an
incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed
upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to
the RAM would otherwise be expected.
DS1216 SmartWatch RAM/SmartWatch ROM
Figure 1. SmartWatch Comparison Register Definition
NONVOLATILE CONTROLLER OPERATION The DS1216 SmartWatch performs circuit functions required to make a CMOS RAM nonvolatile. First, a
switch is provided to direct power from the battery or VCC supply, depending on which voltage is greater.
This switch has a voltage drop of less than 0.2V. The second function that the SmartWatch provides is
power-fail detection, which occurs at VTP. The DS1216 constantly monitors the VCC supply. When VCC goes out of tolerance, a comparator outputs a power-fail signal to the chip-enable logic. The third function
accomplishes write protection by holding the chip-enable signal to the memory within 0.2V of VCC or
battery. During nominal power-supply conditions, the memory chip-enable signal will track the chip-
enable signal sent to the socket with a maximum propagation delay of 7ns for the 5V and 12ns for the
3.3V version.
FRESHNESS SEAL Each DS1216 is shipped from Dallas Semiconductor with its lithium energy source disconnected,
ensuring full energy capacity. When VCC is first applied at a level greater than the lithium energy source
is enabled for battery-backup operation.
DS1216 SmartWatch RAM/SmartWatch ROM
SMARTWATCH REGISTER INFORMATION The SmartWatch information is contained in eight registers of 8 bits, each of which is sequentially
accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When
updating the SmartWatch registers, each must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 3.
Data contained in the SmartWatch registers is in binary-coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
AM-PM/12-/24-MODE Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the second 10-hour bit (20 to 23 hours).
OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RST and oscillator functions. Bit 4 controls the
RST (pin 1). When the RST bit is set to logic 1, the RST input pin is ignored. When the RST bit is set to
logic 0, a low input on the RST pin will cause the SmartWatch to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set
to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the
factory set to logic 1.
ZERO BITS Registers 1 to 6 contain one or more bits that always read logic 0. When writing these locations, a logic 1
or 0 is acceptable.
ADDITIONAL INFORMATION Refer to Application Note 52: Using the Dallas Phantom Real-Time Clocks (available on our website at
/RTCapps) for information about using regarding optional modifications and the
phantom clock contained within the SmartWatch.
DS1216 SmartWatch RAM/SmartWatch ROM
Figure 2. Reset and Memory Density Options The RST pin on the controller has an internal pullup resistor. To disable the RST function, the trace
between pin 1 on the socket and pin 13 on the controller can be cut. In this case, the socket will ignore the
RST input, preventing address transitions from resetting the pattern match, even if the RST bit is enabled.
On the DS1216B and DS1216D, the two VCC pins are connected together on the PC board. The switched
VCC from the controller is connected to the two VCC pins that connect to the inserted RAM. No
modifications are required if the lower density RAM is used. To use the higher density RAM, the trace by
the lower density RAM VCC pin, identified by a hash mark labeled “U,” must be cut. The two square-
metal pads, labeled “G,” must be shorted together. This disconnects switched VCC from the pin going to
the inserted RAM, and connects it to the corresponding address input pin for the higher density RAM.
