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DP8481N
TTL to 10k ECL Level Translator with Latch
TL/F/5862
DP8481
TTL
10k
ECL
Level
Translator
with
Latch
June 1986
DP8481 TTL to 10k ECL Level Translator with Latch
General Description
This circuit translatesTTL input levelsto ECL output levels
and provides afall-throughlatch.The outputsare gatedwith providingfor wire ORingof outputs.The strobe andchip
select inputs operateat ECL levels.
Features 16-pin flat-packorDIP ECL control inputsCS providedfor wire ORingof outputbus 10k ECLI/O compatible3.0ns typical propagation delay
Logic and Connection Diagram
Dual-In-Line Package
TL/F/5862–1
Top View
Truth Table STR CS L H L H HH X L
Hehighlevel (most positive)
Lelow level(most negative)
Xedon’tcare
OrderNumber
DP8481F, DP8481Jor DP8481N
SeeNS Package
F16B, J16Aor N16A
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
