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DP83846NSCN/a18avaiDsPHYTER ぱSingle 10/100 Ethernet Transceiver


DP83846 ,DsPHYTER ぱSingle 10/100 Ethernet TransceiverFeaturesThe DP83846A is a full feature single Physical Layer ■ IEEE 802.3 ENDEC, 10BASE-T transceiv ..
DP83846A ,Single 10/100 Ethernet TransceiverFeaturesThe DP83846A is a full feature single Physical Layer ■ IEEE 802.3 ENDEC, 10BASE-T transceiv ..
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DS89C450-ENL+ ,Ultra-High-Speed Flash Microcontrollersapplications will experience a Dual Data Pointers with Automatic speed improvement up to 10x. At 1 ..


DP83846
DsPHYTER ぱSingle 10/100 Ethernet Transceiver
DP83846A DsPHYTER® — Single 10/100 Ethernet Transceiver
Preliminary

April 2000
DP83846A DsPHYTER
® — Single 10/100 Ethernet Transceiver
General Description

The DP83846Aisa full feature single Physical Layer
device with integrated PMD sublayersto support both
10BASE-T and 100BASE-TX Ethernet protocols over Cat-
egory3 (10 Mb/s)or Category5 unshielded twisted pair
cables.
The DP83846Ais designed for easy implementationof
10/100 Mb/s Ethernet homeor office solutions.It interfaces Twisted Pair media viaan external transformer. This
device interfaces directlyto MAC devices through the IEEE
802.3u standard Media Independent Interface (MII) ensur-
ing interoperability between products from different ven-
dors.
The DP83846A utilizeson chip Digital Signal Processing
(DSP) technology and digital Phase Lock Loops (PLLs)for
robust performance under all operating conditions,
enhanced noise immunity, and lower external component
count when compared to analog solutions.
System Diagram

Status
10BASE-T
100BASE-TXMII
25 MHz
Typical DsPHYTER application

Ethernet MAC
Magnetics
RJ-45
Clock LEDs
DP83846A

10/100 Mb/s
DsPHYTER
Features
IEEE 802.3 ENDEC, 10BASE-T transceivers and filters IEEE 802.3u PCS, 100BASE-TX transceivers and filters IEEE 802.3 compliant Auto-Negotiation Output edge rate control eliminates external filtering for
Transmit outputs BaseLine Wander compensation 5V/3.3V MAC interface IEEE 802.3u MII (16 pins/port) LED support (Link, Rx, Tx, Duplex, Speed, Collision) Single register access for complete PHY status 10/100 Mb/s packet loopback BIST (Built in Self Test) Low-power 3.3V, 0.35um CMOS technology 5V tolerant I/Os 80-pin LQFP package (12w) x (12l) x (1.4h) mm
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