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DP83843BVJE
PHYTER
DP83843BVJE PHYTERJuly 1999
DP83843BVJE PHYTER
General DescriptionThe DP83843BVJEisafull feature Physical Layer device
with integrated PMD sublayersto support both 10BASE-T
and 100BASE-X Ethernet protocols.
This VLSI deviceis designedfor easy implementationof
10/100 Mb/s Ethernet LANs.It interfaces directlyto Twisted
Pair media through an external transformerorto fiber
media via industry standard electrical/optical fiber PMD
transceivers. This device also interfaces directlyto the
MAC layer through the IEEE 802.3u standard Media Inde-
pendent Interface (MII), ensuring interoperability between
products from different vendors.
The DP83843is designed with National Semiconductor's
advanced CMOS process.Its system architectureis based the integrationof severalof National's industry proven
core technologies: IEEE 802.3 ENDEC with AUI/10BASE-T transceiver
module to provide the 10 Mb/s functions Clock Recovery/GeneratorModules from National'sFast
Ethernet and FDDI products FDDI Stream Cipher scrambler/descrambler for
TP-PMD 100BASE-Xphysicalcodingsub-layer (PCS)and control
logic that integrates the core modules intoa dual speed
Ethernet physical layer controller ANSI X3T12 Compliant TP-PMD Transceiver
technology with Baseline Wander (BLW) compensation
System Diagram10 AND/OR 100 Mb/s
ETHERNET MAC OR
100Mb/s REPEATER
DP8384310/100 Mb/s
ETHERNET PHYSICAL LAYER
STATUS
LEDS
GNETICS
RJ-45
10BASE-T
100BASE-TX
MII
10BASE-T or
CONTROLLER
100BASE-TX
100BASE-FX/
CLOCK
25 MHz
AUI
Features IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
and built-in filters IEEE 802.3u 100BASE-TX compatible - directly drives
standard Category 5 UTP, no need for external
100BASE-TX transceiver Fully Integrated and fully compliant ANSI X3.263 TP-
PMD physical sublayer which includes adaptive equal-
ization and BLW compensation IEEE 802.3u 100BASE-FX compatible- connects direct-
ly to industry standard Electrical/Optical transceivers IEEE 802.3u Auto-Negotiation for automatic speed se-
lection IEEE 802.3u compatible Media Independent Interface
(MII) with Serial Management Interface Integrated high performance 100 Mb/s clock recovery
circuitry requiring no external filters Full Duplex support for 10 and 100 Mb/s data rates MII Serial 10 Mb/s mode Fully configurable node/switch and 100Mb/s repeater
modes Programmable loopback modesfor flexible system diag-
nostics Flexible LED support Single register access to complete PHY status MDIO interrupt support Individualized scrambler seed for 100BASE-TX applica-
tions using multiple PHYs Low power consumption for multi-port applications Small footprint 80-pin PQFP package
