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DM74S74
Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear and Complementary Outputs
TL/F/6457
DM54S74/DM74S74
Dual
Positive-Edge-Triggered
Flip-Flops
with
Preset,
Clear,
and
Complementary
Outputs
June 1989
DM54S74/DM74S74
Dual Positive-Edge-TriggeredD Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
geredD flip-flopswith complementary outputs.The informa-
tionontheD inputis acceptedbythe flip-flopsonthe posi-
tive going edgeof theclock pulse.The triggeringoccursata
voltage levelandisnot directly relatedtothe transition timethe rising edgeofthe clock. The dataontheD input may changed whilethe clockislowor high without affecting
the outputsas longas setup andhold timesarenot violated.low logic levelonthe presetor clear inputswillsetor
resetthe outputs regardlessofthe logic levelsofthe other
inputs.
Connection Diagram
Dual-In-Line Package
TL/F/6457–1
Order Number DM54S74J, DM54S74W, DM74S74MorDM74S74N
SeeNS Package Number J14A,M14A, N14Aor W14B
Function Table
Inputs Outputs CLR CLK D Q Q X X H L X X L H X X H* H* u HH L u LL H L X Q0 Q0 eHigh Logic Levele EitherLoworHigh Logic LeveleLow Logic Levele Positive-going TransitioneThis configurationis nonstable;thatis,itwillnot persist wheneitherthe
preset and/orclear inputs returntoits inactive (high) level.eThe outputlogiclevel ofQbeforethe indicatedinput conditionswere established.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
