Partno |
Mfg |
Dc |
Qty |
Available | Descript |
DM74S51J |
|
N/a |
1656 |
|
|
DM74S51N ,Dual 2-Wide 2-Input AND-OR-INVERT GateGeneral DescriptionThis device contains two independent combinations ofgates each of which performs ..
DM74S570AJ ,45 ns, (512 x 4) 2048-bit TTL PROMBlock Diagram
MIT ARRAY
M x Q
MEMORV MATRIX
DECDDER
mm
BUFFER ca 02 tll no
TL/D/91B9 ..
DM74S570N ,55 ns, (512 x 4) 2048-bit TTL PROMElectrical Characteristics (Note1)
Symbol Parameter Conditions DM545570 DM74S570 Units
Min Typ Ma ..
DM74S571AJ ,45 ns, (512 x 4) 2048-bit TTL PROMFeatures
I Advanced titanium-tungsten (Ti-W) fuses
I Schottky-clamped for high speed
Address ..
DM74S571AN ,45 ns, (512 x 4) 2048-bit TTL PROMBlock Diagram
20488” ARRAV
M l 32
MEMORY MATRIX
DECODER
ENABLE
BUFFER
00
TL/D/9713- ..
DS2506 ,64 kbit Add-Only Memoryblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2506 ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..
DS2506S ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..