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DM74S474ANNSN/a789avai45 ns, (512 x 8) 4096-bit TTL PROM
DM74S474NNSN/a34avai65 ns, (512 x 8) 4096-bit TTL PROM


DM74S474AN ,45 ns, (512 x 8) 4096-bit TTL PROMBlock Diagram A8 A7 M A5 M A3 4MB" ARRAY M x M MEMORY MAYRIX DECUUER A? A! A0 ..
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DM74S570N ,55 ns, (512 x 4) 2048-bit TTL PROMElectrical Characteristics (Note1) Symbol Parameter Conditions DM545570 DM74S570 Units Min Typ Ma ..
DM74S571AJ ,45 ns, (512 x 4) 2048-bit TTL PROMFeatures I Advanced titanium-tungsten (Ti-W) fuses I Schottky-clamped for high speed Address ..
DS2505P+ ,16Kb Add-Only MemoryFEATURES PIN ASSIGNMENT  16384 bits Electrically Programmable Read TSOC PACKAGE TO-92Only Memory ..
DS2506 ,64 kbit Add-Only Memoryblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2506 ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..
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DM74S474AN-DM74S474N
60 ns, (512 x 8) 4096-bit TTL PROM
DM54S474/DM74S474
I National
i Semiconductor
DM54/74S474
(512 x 8) 4096-Bit TTL PROM
General Description
This Schottky memory is organized in the popular 512
words by 8 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled. the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all loca-
tions. A high may be programmed into any selected location
by following tho programming instructions.
F eatu res
I: Advanced titanium-tungsten (Ti-W) fuses
ll Schottky-clamped for high speed
Address access-35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
" PNP inputs for reduced input loading
a All DC and AC parameters guaranteed over
temperature
n Low voltage TRI-SAFETM programming
n TRI-STATE© outputs
Block Diagram
4M8" ARRAY
MEMORY MATRIX
UECIIDER
ENABLE
ilhtf 07 us 05 04 03 tlt
Pin Names
AO-AB Addresses
a Tra G3, G4 Output Enables
GND Ground
NC No Connection
Q0-O7 Outputs
W Vcc Power Supply
01 (10
TL/D/9714-1
Connection Diagrams
Dual-ln-Llne Package
A7-1 1 24 -a
M- 2 23 -A8
A5- 3 22 -tlc
M- 4 21 .-trt
M- 5 20 ~67
112- 6 19 -03
AI- 7 18 ~61
A0- a 17 -07
tlo-. 9 16 -tl6
Qt-- 10 15 -tl5
tl2- 11 14 -04
tmo-. 12 13 -o
TL/D/9714-2
Top View
Order Number DM54/74S474J, 474AJ, 4743.1,
DM74S474N, 474AN, 474BN
See NS Package Number J24A or N24A
Ordering Information
Commercial Temp Range ttt'C to + 70'C)
Plastic Leaded Chip Carrier (PLCC)
2 3 '2 2 >82 2
t I l l l l I
4 3 2 t 28 27 26
M--5 25-61
As-s 24-ii-2
A2-7 23-63
111-3 22 -c4
A0-9 21-111:
NC-io 20-07
00-11 19 ~05
12 13 14 15 1s 17 18
I ‘Fl l l I l
- N ca U '0 " I!)
O O p, = 0 O O
TL/D/9714-3
Toleew
Order Number DM74S474V, 474AV, 474BV
See NS Package Number V28A
Military Temp Range (-55"C to + 125°C)
Parameter/Order Number Max Access Time (ns) Parameter/Order Number Max Access Time (ms)
DM74S474AJ 45 DM548474AJ 60
DM74S474BJ 35 DM54S474BJ 50
DM74S474J 65 DM54S474J 75
DM74S474AN 45
DM74S474BN 35
DM74S474N 65
DM74S474AV 45
DM74S474BV 35
DM74S474V 65
flt’S’PlWG/VLVSVSWG
DM54S474/DM74S474
Absolute Maximum Ratings (Note1)
Operating Conditions
If Mllitary/Aerospace speeitled devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (Vcc)
Office/Dlslrlbulors for availability and specifications. Military 4.50 5.50 V
Supply Voltage (Note 2) - 0.5V to + 7.0V Commercial 4.75 5.25 V
Input Voltage (Note 2) - 1 .2V to + 5.5V Ambient Temperature (TA)
Output Voltage (Note 2) --0.5V to + 5.5V Military _ 55 + 125 "C
Storage Temperature - 65°C to + 150°C Commercial 0 + 70 "C
Lead Temp. (Soldering, 10 seconds) 300°C Logical "ty' Input Voltage 0 0.8 V
ESD to be determined Logical "I" Input Voltage 2.0 5.5 V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be permammtly damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note1)
Symbol Parameter Conditions DM54S474 DM74S474 Units
Min Typ Max Min Typ Max
lit. Input Load Current Vcc = Max, VIN I 0.45V -80 -250 -80 -250 p
IIH Input Leakage Current Vcc = Max, VIN = 2.7V 25 25 pA
Vcc = Max,V|N = 5.5V 1.0 1.0 mA
VOL Low Level OutputVoltage Vcc = Min, tor, = 16 mA 0.35 0.50 0.35 0.45 V
" Low Level Input Voltage 0.80 0.80 V
VIH High Level Input Voltage 2.0 2.0 V
Vc Input Clamp Voltage VCC = Min, 'IN = -18 mA -0.8 -1.2 -0.8 -1.2 V
th Input Capacitance Vcc = 5.0V, VIN = 2.0V f
TA = 290.1 MHz 4.0 4.0 pF
Co OutputCapacitance Vcc = 5.0V, vo = 2.0V 6 0 6 o F
TA == 25°C,1 MHz, Outputs off . . p
be Power Supply Current Vcc = Max, Inputs Grounded 1 15 170 1 1 5 170 m A
All Outputs Open
los Short Circuit Vo = 0V, VCC = Max _ - - -
Output Current (Note 2) 20 70 20 70 mA
'02 Output Leakage Vcc = Max, V0 = 0.45V to 2.4V +50 + 50 p.A
(TRI-STATE) Chip Disabled - 50 - 50 " A
VOH Output Voltage High lor, = - 2.0 mA 2.4 3.2 V
IQ... = -6.5 mA 2.4 3.2 V
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vcc -- 5.0V and TA _- 25"C.
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (0°C to + 70°C)
Symbol ie,',,',? Parameter DM74S474 DM748474A DM74S474B Units
ymbol Min Typ Max Min Typ Max Min Typ Max
TAA TAVQV Address Access Time 40 65 25 45 25 35 ns
TEA TEVQV Enable Access Time 20 35 15 25 15 25 ns
TER TEXQX Enable Recovery Time 20 35 15 25 15 25 ns
TZX TEVQX Output Enable Time 20 35 15 25 15 25 ns
TXZ TEXQZ Output Disable Time 20 35 15 25 15 25 ns
MILITARY TEMP RANGE (- 55°C to + 125°C)
Symbol :EDEC Parameter DM54S474 DM54S474A DM54S474B Units
ymbol Min Typ Max Min Typ Max Min Typ Max
TAA TAVQV Address Access Time 40 7O 25 60 25 50 ns
TEA TEVQV Enable Access Time 20 40 15 35 15 35 ns
TER TEXQX Enable Recovery Time 20 40 15 35 15 35 ns
TZX TEVQX Output Enable Time 20 4O 15 35 15 35 ns
TXZ TEXQZ Output Disable Time 20 4O 15 35 15 35 ns
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the program-
ming tests in the final product. A ROM pattern is also per-
manentiy fixed in the additional circuitry and coded to pro-
vide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and en-
able gates. All test circuits are available at both water and
assembled device levels to allow 100% functional and para-
metric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PROMs are subject-
ed to an on-going reliability evaluation by the Reliability As-
surance Department. These evaluations employ accelerat-
ed life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and ther-
mal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configura-
tions is excellent.
TITAMUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to pro-
gram efficiently with only 10.5V applied. The high perform-
ance and reliability of these PROMs are the result of fabrica-
tion by a Schottky bipolar process, of which the titanium-
tungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable Iong-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire oper-
ating ranges of Vcc and temperature.
VLVSVLINO/VUSVSWCI
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
DM74S474AV - product/dm74s474av?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM74S474AN - product/dm74s474an?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
DM74S474J - product/dm74s474j?HQS=T|—nu|I-nulI-dscatalog-df—pf—nuII-wwe
DM74S474BV - product/dm74s474bv?HQS=T|—null-nulI-dscatalog-df-pf-nuII-wwe
DM74S474BN - product/dm74s474bn?HQS=T|-nu|l-nu|l-dscatalog-df-pf—nuII-wwe
DM74S474BJ - productldm74s474bj?HQS=T|—nul|-null-dscatalog-df—pf—nuII-wwe
DM54S474J - product/dm54s474j?HQS=Tl-nu|I-nulI-dscatalog-df—pf—nuII-wwe
DM74S474AJ - product/dm74s474aj?HQS=T|—nuII-nulI-dscatalog-df—pf—nuII-wwe
DM74S474N - product/dm74s474n?HQS=T|-null-null-dscatalog-df-pf-null-wwe
DM74S474V - product/dm74s474v?HQS=Tl-nu|I-nuIl-dscatalog-df-pf-nulI-wwe
DM54S474AJ - product/dm54s474aj?HQS=T|—nulI-nulI-dscatalog-df—pf—nuII-wwe
DM54S474BJ - product/dm54s474bj?HQS=T|—nuII-nulI-dscatalog-df—pf—nuII-wwe
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