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DM74S194NNSCN/a25avai7 V, 4-bit bidirectional universal shift register
DM74S194NNSN/a128avai7 V, 4-bit bidirectional universal shift register


DM74S194N ,7 V, 4-bit bidirectional universal shift registerfeatures a system designer may want in a shift register; they feature parallel inputs, parallel ou ..
DM74S194N ,7 V, 4-bit bidirectional universal shift registerElectrical Characteristics over recommended operating tree air temperature (unless otherwise noted) ..
DM74S195N ,7 V, 4-bit parallel access shift registerElectrical Characteristics over recommended operating free air temperature (unless otherwise noted) ..
DM74S20N ,Dual 4-Input NAND GateGeneral DescriptionThis device contains two independent gates each of whichperforms the logic NAND ..
DM74S240N ,Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesThese buffers/line drivers are designed to improve both the

DM74S194N
7 V, 4-bit bidirectional universal shift register
National .
1 Semiconductor
DM54S194/DM74S194
4-Bit Bidirectional Universal Shift Registers
General Description
These bidirectional shift registers are designed to incorpo-
rate virtually all of the features a system designer may want
in a shift register; they feature parallel inputs, parallel out-
puts, right-shitt and lett-shitt serial inputs, operating-mode-
control inputs, and a direct overriding clear line. The register
has tour distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction QA toward OD)
Shift left (in the direction thy toward 0A)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, SO
and SI, high. The data are loaded into the associated flip.
flops and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibit-
Shift right is accomplished synchronously with the rising
edge of the clock pulse when so is high and S1 is low.
Serial data for this mode is entered at the shitt-right data
input. When so is low and S1 is high, data shifts left syn-
chronously and new data is entered at the shift-left serial
input.
Clocking of the flip-flop is inhibited when both mode control
inputs are low.
Features
I: Parallel inputs and outputs
I: Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
a Positive edge-triggered clocking
a Direct overriding clear
rt Typical clock frequency 105 MHz
a Typical power dissipation 425 mW
Connection Diagram
Dual-In-Llne Package
ouwurs
Vcc aa Q3 A: On CLOCK St so
" " " " " " 10 I9
1 2 a 4 s e 7 Is
CLEAR smn A a c D SHIFT one
mam LEFT
SERIAL PARALLEL ms SERIAL
INPUT INPUT
TL/F/6475-1
Order Number DM54S194J or DM74S194N
Sett NS Package Number J16A or N16E
Absolute Maximum Ratings (Note)
If Mllltary/Aerospace specified devlces are required,
please contact the National Sttmlettttdutttttr Sales
Offlce/Dlatrlbutors for avallablllty and tttttremains.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54S -55'C to + 125°C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions " table will define
the Conditions for actual device operation.
Storage Temperature Range
0°C to + 70'C
- 65°C to + 150'C
Recommended Operating Conditions
Symbol Parameter DM54S194 DM74S194 Units
Mln Nom Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.8 0.8 V
10H High Level Output Current -- 1 -I mA
IOL Low Level Output Current 20 20 mA
fCLK Clock Frequency (Note I) 0 105 70 0 105 70 MHz
fCLK Clock Frequency (Note 2) 90 60 90 60 MHz
tw Pulse Width Clock
Note 3) ns
( Cltsar 12 12
tsu Setup Time Mode 1 1 1 1
(Note 3) Data 5
tH Hold Time (Note 3) 3 ns
tREL Clear Release Time (Note 3) 9 ns
TA Free Air Operating Temperature - 55 125 0 70 "C
Note 1: CL = 15 pF, Rt. ' 2300, TA = 25t and Vcc = 5v.
Note 2: Ct = 50 pF, RL = 2809. TA = 25'C and Vcc = 5V.
Note 3: TA = 25'C and Vcc = 5V.
Electrical Characteristics over recommended operating lree air temperature (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 4)
VI lnputCIamp Voltage Vcc = Min, 1. = --18 mA --t.2 V
VOH High LevelOutput VCC = Min, IOH = Max DM54 2.5 3.4
Voltage V = Max V = Min V
IL , W DM74 a7 3.4
VOL Low Level Output Vcc = Min, kat. = Max 0 5 V
Voltage Ihr, = Min, " = Max .
ll InputCurrent © Max VCC = Max,)h = 5.5V
Input Voltage
IIH High Level InputCurrent Vcc = Max, V. = 2.7V 50 pA
Ist. Low Level lnputCurrent Vcc = Max, V. = 0.5V --2 mA
los Short Circuit Vcc = Max DM54 --40 _ 100
Output Current (Note 5) mA
DM74 -40 - 100
106 Supply Current Vcc = Max (Note 6) 85 135 mA
Note 4: " typicals are at Vcc; = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Note 6: mm all outputs open. inputs A through D grounded, and 4.5V applied to so, SI, CLEAR, and the SERIAL inputs, ICC is tested with a momentary ground,
then 4.5V applied to CLOCK.
Switching Characteristics at Vcc = 5V and TA = 25°C (See Section 1 tor Test Waveforms and Output Load)
RL = 2800
From (Input)
Symbol Parameter To (Output) th. --- " pF CL == 50 pF Unlla
Min Max Mln Max
fMAX Maximum Clock Frequency 70 60 MHz
tpLH Propagation Delay Time Clock 1 2 15 ns
Low to High Level Output to Q
tpHL Propagation Delay Time Clock
High to Low Level Output to 0 16.5 20 ns
tpHL Propagation Delay Time Clear
High to Low Level Output to Q 18.5 23 ns
Function Table
Inputs Outputs
Clear Mode Clock Sorlal Parallel thx th, th: thr
m so Left Right A B c D
L X X X X X X X X X L L L L
H X X L X X X X X X QAO thm 000 000
H H H t X X a b c d a b c d
H L H t x H x x x x H QAn than Qo,
H L H t X L X X X X L QAn then Am
H H L t H X X X X X QBn an QDn H
H H L t L X X X X X thr, ao, thm L
H L t. X X X X X X X 0A0 tho thoo thoo
H --- High Level (steady state). L = Low Level (steady state), X '= Don't Care (any Input. includlng transitions).
t = Transition from low to high level.
a, b, c. d = The level of steady state input at inputs A, B, C, or D, respectively.
OM. tho av, 000 = The level ot th, th, Qc, or tho, respectively, before the indicated steady Mate input conditions were established?
tu,, (Jan. thm, Qua '= The level of 0A. 03. A; respectively, before the most recent t transition of the clock.
Logic Diagram
PARALLEL "UT:
MALL“. W5
TLtFf6475-2
Timing Diagram
MODE so
CONTROL 4
INPUTS SI
SERIAL R
DATA _
INPUTS L
PARALLEL
DATA ,
INPUTS
OUTPUTS 4
Typlcal Clear, Load, Right-Shift, Left-Shlft, Inhlbit, and Clear Sequences
CLEAR LOAD
SHIFT RIGHT SHIFT LEFT INHlBlT
TL/F/6475-3
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