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DM74LS138MXFAIRCHILDN/a2431avai 3-to-8 Line Decoder/Demultiplexer
DM74LS138MXNSCN/a2500avai 3-to-8 Line Decoder/Demultiplexer
DM74LS138MXFAIN/a2412avai 3-to-8 Line Decoder/Demultiplexer


DM74LS138MX , 3-to-8 Line Decoder/Demultiplexerapplications, requiring very short propagation delay times.Data transmission systemsIn high-perform ..
DM74LS138MX , 3-to-8 Line Decoder/DemultiplexerFeaturesThese Schottky-clamped circuits are designed to be used ■ Designed specifically for high sp ..
DM74LS138MX , 3-to-8 Line Decoder/Demultiplexerapplications.The DM74LS139 comprises two separate two-line-to-four-line decoders in a single packag ..
DM74LS138N ,Decoders/DemultiplexersFeaturesThese Schottky-clamped circuits are designed to be used Designed specifically for high spe ..
DM74LS138SJ ,Decoder/Demultiplexerapplications, requiring very short propagation delay times.Data transmission systemsIn high-perform ..
DM74LS139M ,Decoders/DemultiplexersFeaturesused to minimize the effects of system decoding. WhenYDesigned specifically for high speed: ..
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DM74LS138MX
3-to-8 Line Decoder/Demultiplexer
DM74LS138 • DM74LS139 Decoder/Demultiplexer August 1986 Revised March 2000 DM74LS138 • DM74LS139 Decoder/Demultiplexer General Description Features These Schottky-clamped circuits are designed to be used � Designed specifically for high speed: in high-performance memory-decoding or data-routing Memory decoders applications, requiring very short propagation delay times. Data transmission systems In high-performance memory systems these decoders can � DM74LS138 3-to-8-line decoders incorporates 3 enable be used to minimize the effects of system decoding. When inputs to simplify cascading and/or data reception used with high-speed memories, the delay times of these � DM74LS139 contains two fully independent 2-to-4-line decoders are usually less than the typical access time of the memory. This means that the effective system delay decoders/demultiplexers introduced by the decoder is negligible. � Schottky clamped for high performance The DM74LS138 decodes one-of-eight lines, based upon � Typical propagation delay (3 levels of logic) the conditions at the three binary select inputs and the DM74LS138 21 ns three enable inputs. Two active-low and one active-high DM74LS139 21 ns enable inputs reduce the need for external gates or invert- � Typical power dissipation ers when expanding. A 24-line decoder can be imple- mented with no external inverters, and a 32-line decoder DM74LS138 32 mW requires only one inverter. An enable input can be used as DM74LS139 34 mW a data input for demultiplexing applications. The DM74LS139 comprises two separate two-line-to-four- line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applica- tions. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify sys- tem design. Ordering Code: Order Number Package Number Package Description DM74LS138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS139M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS139N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006391
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