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74LS132N/a602avaiQuad 2-Input NAND Gate with Schmitt Trigger Input
DM74LS132SJNSN/a1000avaiQuad 2-Input NAND Gate with Schmitt Trigger Input


DM74LS132SJ ,Quad 2-Input NAND Gate with Schmitt Trigger InputGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NAND ..
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DS2148G+ ,5V E1/T1/J1 Line InterfacePIN DESCRIPTION 10 3 HARDWARE MODE ....... 23 3.1 REGISTER MAP ........23 3.2 PARALLEL PORT OPERATI ..
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DS2148GN ,5V E1/T1/J1 Line Interfaceapplications. The crystal-less onboard jitter attenuator requires only a 2.048MHz MCLK for both E1 ..
DS2148T ,5V E1/T1/J1 Line InterfaceTABLE OF CONTENTS 1. LIST OF FIGURES. 4 2. LIST OF TABLES .. 5 3. INTRODUCTION... 6 3.1 DOCUMENT R ..


74LS132-DM74LS132SJ
Quad 2-Input NAND Gate with Schmitt Trigger Input
DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Input August 1986 Revised March 2000 DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hystere- sis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. Ordering Code: Order Number Package Number Package Description DM74LS132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS132N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LL H LH H HL H HH L H = HIGH Logic Level L = LOW Logic Level © 2000 DS006389
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