DM74LS109AMX , Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary OutputsDM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs ..
DM74LS109AMX , Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered J-K flip-flops wit ..
DM74LS109AN ,Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary OutputsFeaturesnotdirectlyrelatedtothetransitiontimeoftherisingedgeofYAlternate Military/Aerospace device ..
DM74LS10M ,Triple 3-Input NAND GatesGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic NAN ..
DM74LS10M ,Triple 3-Input NAND GatesFeaturesYAlternate Military/Aerospace device (54LS10) is avail-Thisdevicecontainsthreeindependentga ..
DM74LS10N ,Triple 3-Input NAND GateDM74LS10 Triple 3-Input NAND GateAugust 1986Revised March 2000DM74LS10Triple 3-Input NAND Gate
DS21349Q+ ,3.3V T1/J1 Line Interface UnitAPPLICATIONS Four CSU Filters from 0dB to -22.5dB Routers Transmit/Receive Performance Monitors ..
DS21352 ,3.3V DS21352 and 5V DS21552 T1 Single Chip TransceiversFUNCTIONAL DESCRIPTION....83.2 DOCUMENT REVISION HISTORY...104.
DS21352DK ,T1 Single-Chip Transceiver Design Kit Daughter CardFEATURES The DS21352 design kit is an easy-to-use evaluation Demonstrates Key Functions of DS2135 ..
DS21352G ,3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers3.3V DS21352 and 5V DS21552T1 Single-Chip Transceivers
DS21352L ,3.3V DS21352 and 5V DS21552 T1 Single-Chip TransceiversFEATURES PIN ASSIGNMENT Complete DS1/ISDN–PRI/J1 transceiver functionality Long and Short haul L ..
DS21352L+ ,3.3V DS21352 and 5V DS21552 T1 Single Chip TransceiversFUNCTIONAL DESCRIPTION....83.2 DOCUMENT REVISION HISTORY...104.
DM74LS109AMX
Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary Outputs
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regard- less of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK J K QQ LH X X X H L HL X X X L H L L X X X H (Note 1) H (Note 1) HH ↑ LL L H HH ↑ H L Toggle HH ↑ LH Q Q 0 0 HH ↑ HH H L HH L X X Q Q 0 0 H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↑ = Rising Edge of Pulse Q = The output logic level of Q before the indicated input conditions were 0 established. Toggle = Each output changes to the complement of its previous level on each active transition of the clock pulse. Note 1: This configuration is nonstable; that is, it will not persist when pre- set and/or clear inputs return to their inactive (HIGH) state. © 2000 DS006368
