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DM74AS874NTFAIN/a2avaiDual 4-Bit D-Type Edge-Triggered Flip-Flops
DM74AS874NTNSN/a82avaiDual 4-Bit D-Type Edge-Triggered Flip-Flops
DM74AS874WMFAIN/a595avaiDual 4-Bit D-Type Edge-Triggered Flip-Flops
DM74AS874WMXFAIN/a12avaiDual 4-Bit D-Type Edge-Triggered Flip-Flops


DM74AS874WM ,Dual 4-Bit D-Type Edge-Triggered Flip-FlopsDM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-FlopOctober 1986Revised July 2003DM74AS874Dual 4-Bi ..
DM74AS874WMX ,Dual 4-Bit D-Type Edge-Triggered Flip-FlopsFeaturesThese dual 4-bit inverting registers feature totem-pole 3-

DM74AS874NT-DM74AS874WM-DM74AS874WMX
Dual 4-Bit D-Type Edge-Triggered Flip-Flops
DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop October 1986 Revised July 2003 DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop General Description Features These dual 4-bit inverting registers feature totem-pole 3-Switching specifications at 50 pF STATE outputs designed specifically for driving highly-Switching specifications guaranteed over full tempera- capacitive or relatively low-impedance loads. The high- ture and V range CC impedance state and increased high-logic-level drive pro- Advanced oxide-isolated, ion-implanted Schottky TTL vide these registers with the capability of being connected process directly to and driving the bus lines in a bus-organized sys- 3-STATE buffer-type outputs drive bus lines directly tem without need for interface or pull-up components. They are particularly attractive for implementing buffer registers,Space saving 300 mil wide package I/O ports, bidirectional bus drivers, and working registers. Bus structured pinout The eight flip-flops of the DM74AS874 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package, while all outputs are on the other side. Ordering Code: Order Number Package Number Package Description DM74AS874WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74AS874NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2003 DS006331
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