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DM54191JNSN/a10avaiSynchronous Up/Down 4-Bit Binary Counter with Mode Control
DM74191NNSN/a790avaiSynchronous Up/Down 4-Bit Binary Counter with Mode Control
DM74191NNSCN/a81avaiSynchronous Up/Down 4-Bit Binary Counter with Mode Control


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DM54191J-DM74191N
Synchronous Up/Down 4-Bit Binary Counter with Mode Control
TL/F/6562
54191/DM54191/DM74191
Synchronous
Up/Down
4-Bit
Binary
Counter
with
Mode
Control
June 1989
54191/DM54191/DM74191 Synchronous Up/Down
4-Bit Binary Counter with Mode Control
General Description
This circuitisa synchronous, reversible, up/down counter.
The191isa 4-bit binary counter. Synchronous operationis
providedby havingall flip-flops clocked simultaneouslyso
thatthe outputs change simultaneously whenso instructedthe steering logic. This modeof operation eliminatesthe
output counting spikes normally associated with asynchro-
nous (ripple clock) counters.
The outputsofthefour master-slave flip-flopsare triggereda low-to-high level transitionofthe clock input,ifthe
enable inputislow.A highatthe enable input inhibits count-
ing. Level changesat eitherthe enable inputorthe down/ input shouldbe made only whenthe clock inputis high.
The directionofthe countis determinedbythe levelofthe
down/up input. Whenlow,the counter countsupand when
high,it counts down.
This counteris fully programmable;thatis,the outputs may presetto either levelby placingalowonthe load input
and enteringthe desired dataatthe data inputs.The output
will change independentofthe levelofthe clock input. This
feature allowsthe counterstobe usedas modulo-Ndividers simply modifyingthe count length withthe preset inputs.
The clock, down/up,and load inputsare bufferedto lower
the drive requirement; which significantly reducesthe num-
berof clock drivers, etc., requiredfor long parallel words.
Two outputs have been made availableto performthe cas-
cading function: ripple clockand maximum/minimum count.
The latter output producesa high-level output pulse witha
duration approximately equaltoone complete cycleofthe
clock whenthe counter overflowsor underflows.The ripple
clock output producesa low-level output pulse equalin
widthtothe low-level portionofthe clock input whenan
overflowor underflowcondition exists.The counterscanbe
easily cascadedby feedingthe ripple clock outputtothe
enable inputofthe succeeding counterif parallel clockingis
used,ortothe clock inputif parallel enablingis used. The
maximum/minimum count output canbe usedto accom-
plish look-aheadfor high-speed operation.
Features Single down/up count controlline Count enable control input Ripple clock outputfor cascading Asynchronously presettable with load control Parallel outputs Cascadablefor n-bit applications Alternate Military/Aerospace device (54191)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6562–1
Order Number 54191DMQB,54191FMQB,
DM54191J, DM54191W orDM74191N
SeeNS PackageNumberJ16A, N16Eor W16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
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