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DG5043CJSILICONIXN/a10avaiMonolithic General-Purpose CMOS Analog Switch


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DS1000-100 ,5-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1-TAP 5 - TAP Output NumberV - +5 VoltsCCGND - GroundNC - No ConnectionIN - Inpu ..
DS1000-125 ,5-Tap Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN 1 14 VCC 5 taps equally spaced1IN 8 VCCNC 2 13 N ..
DS1000-150 ,5-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1-TAP 5 - TAP Output NumberV - +5 VoltsCCGND - GroundNC - No ConnectionIN - Inpu ..
DS1000-175 ,5-Tap Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN 1 14 VCC 5 taps equally spaced1IN 8 VCCNC 2 13 N ..
DS1000-200 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1000-25 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..


DG5043CJ
Monolithic General-Purpose CMOS Analog Switch
S1Dual-In-Line
IN1 V– GND VL V+ IN2 S2
Top View
DG5043
Vishay Siliconix
Monolithic General-Purpose CMOS Analog Switch

�������� �������� ������������ 15-V Input Range On-Resistance: <50  Break-Before-Make Switching TTL and CMOS Compatible Improved Signal Headroom Reduced Switching Errors No Shorting of Inputs Simple Interfacing Audio Switching Instrumentation Battery Powered Systems
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The DG5043 solid state analog switch is recommended for
general purpose applications in instrumentation, and process
control. Built on the Vishay Siliconix PLUS-40 high voltage
CMOS process, this device provides ease-of-use and
performance advantages to the system designer. Key
performance features of the DG5043 are 1-s switching, low
power supply requirements, and break-before-make
switching. Each switch conducts equally well in either
direction, when on, and blocks up to 30 V peak-to-peak when
off. Off leakage current is 1-nA maximum. An epitaxial layer
prevents latch up. For new designs, DG403 is recommended.
Logic “0” =  0.8 V
Logic “1” =  2 V
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V+ to V– 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND to V– 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL (GND – 0.3 V) to 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa VS, VD (V–) –2 V to (V+ plus 2 V). . . . . . . . . . . . . . . . . . . . . . .
or 30 mA, whichever occurs first
Current (Any Terminal) Continuous 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package)b
16-Pin Plastic DIPc 470 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes: Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal
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