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DAC8812ICPW from TI, Texas Instruments 55pcs , SSOP-16,16-Bit, Dual Serial Input Multiplying Digital-to-Analog Converter 16-TSSOP -40 to 85
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DAC8812ICPW TI N/a 55
DAC8812ICPW from TI/BB , Texas Instruments 215pcs,16-Bit, Dual Serial Input Multiplying Digital-to-Analog Converter 16-TSSOP -40 to 85
SBAS349F–AUGUST 2005–REVISED JUNE 20165 Device Comparison TableDEVICE MAXIMUM RELATIVE ACCURACY (LSB)DAC8812C ±1DAC8812B ±26 Pin Configuration and FunctionsPW Package16-Pin TSSOPTop ViewR A 1 16 CLKFBV A 2 15 LDACREFI A 3 14 MSBOUTA A 4 13 VGND DDA B 5 12 DGNDGNDI B 6 11 CSOUTV B 7 10 RSREFR B 8 9 SDIFBPin FunctionsPINI/O DESCRIPTIONNO. NAME1 R A I Establish voltage output for DAC A by connecting to external amplifier output.FB2 V A I DAC A reference voltage input pin. Establishes DAC A full-scale output voltage. Can be tied to V pin.REF DD3 I A O DAC A current outputOUT4 A A — DAC A analog groundGND5 A B — DAC B analog groundGND6 I B O DAC B current outputOUT7 V B I DAC B reference voltage input pin. Establishes DAC B full-scale output voltage. Can be tied to V pin.REF DD8 R B I Establish voltage output for DAC B by connecting to external amplifier output.FB9 SDI I Serial data input; data loads directly into the shift register.Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data =10 RS I0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812.Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input11 CS Iregister when CS goes high. Does not affect LDAC operation.12 DGND — Digital ground13 V I Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.DDMSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output14 MSB I equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to groundor V .DDLoad DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers.15 LDAC IAsynchronous active-low input. See Table 2 for operation.16 CLK I Clock input. Positive edge clocks data into shift register.Copyright 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 3Product Folder Links: DAC8812DAC8812SBAS349F–AUGUST 2005–REVISED JUNE 2016 Block Diagram... 134 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision E (March 2016) to Revision F Page• Changed the maximum T value from 125°C to 85°C in the Recommended Operating Conditions table 4A• Changed the name of the input resistance match parameter to Channel-to-channel input resistance match in the

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