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DAC8043U from BB/TI, 8pcs , SOP8,CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER
Partno Mfg Dc Qty Available
DAC8043U BB/TI N/a 8
DAC8043U from BB , 240pcs,CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER
DAC8043U from TI, Texas Instruments 1850pcs,CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER
DAC8043U from TI/BB , Texas Instruments 1pcs,CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER
MAXIMUM RATINGS PIN CONFIGURATIONV to GND . 0V, +7V Top View 8-Pin SOICDDV to GND ..... ±25VREFV to GND ..... ±25VRFBDigital Input Voltage Range .... –0.3V to VDDV 1 8 VREF DDOutput Voltage (Pin 3)... –0.3 V to VDDOperating Temperature RangeAD .......0°C to +70°CR 2 7 CLKFBU, UC ....... –40°C to +85°CJunction Temperature ..... +150°CI 3 6 SRIOUTStorage Temperature....... –65°C to + 150°CLead Temperature (soldering, 10s) . +300° CGND 4 5 LDθ ..... +100°C/WJAθ . +42°C/WJCCAUTION: 1. Do not apply voltages higher than V or less than GNDDDpotential on any terminal except V (Pin 1) and R (Pin 2). 2. The digitalREF FB control inputs are ESD protected: however, permanent damage may occur onunprotected units from high-energy electrostatic fields. Keep units in conduc-tive foam at all times until ready to use. 3. Use proper anti-static handlingprocedures. 4. Absolute Maximum Ratings, unless otherwise noted.DD REF OUT A DAC8043U DAC8043UCPARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITSSTATIC PERFORMANCEResolution N 12 12 Bits(1)Nonlinearity INL ±1 ±1/2 LSB(2)Differential Nonlinearity DNL ±1 ±1/2 LSB(3)Gain Error FSE T = +25°C ±2 ±1 LSBAT = Full Temp Range ±2 ±2 LSBA(5)Gain Tempco TC ±5 ±5 ppm/°CFSEPower Supply Rejection Ratio PSRR ΔV = ±5% ±0.0006 ±0.002 ±0.0006 ±0.002 %/%DD(4)Output Leakage Current I T = +25°C ±5 ±5nALKG AT = Full Temp Range ±100 ±25 nAA(7, 12)Zero Scale Error I T = +25°C 0.03 0.03 LSBZSE AT = Full Temp Range 0.60 0.15 LSBA(8)Input Resistance R 7 11 15 7 11 15 kΩINAC PERFORMANCE(5, 6)Output Current Settling Time t T = +25°C 0.25 1 0.25 1 μsS ADigital-to-Analog Glitch V = 0V 2 20 2 20 nVsREF(5, 10)Energy QI = Load = 100ΩOUTC = 13pFEXTDAC Register Loaded Alternately with all 0s and all 1s(5, 11)Feedthrough Error FT V = 20Vp-p at f = 10kHz 0.7 1 0.7 1 mVp-pREF (V to I ) Digital Input = 0000 0000 0000REF OUTT = +25°CA(5)Total Harmonic Distortion THD V = 6V at 1kHz –85 –85 dBREF RMSDAC Register Loaded with all 1s(5, 13)Output Noise Voltage Density e 10Hz to 100kHz 17 17 nV/√HzNBetween R and IFB OUTDIGITAL INPUTSDigital Input High V 2.4 2.4 VIHDigital Input Low V 0.8 0.8 VIL(9)Input Leakage Current I V = 0V to +5V ±1 ±1 μAIL IN(5, 11)Input Capacitance C V = 0V 8 8 pFIN INANALOG OUTPUTS(5)Output Capacitance C Digital Inputs = V 110 110 pFOUT IHDigital Inputs = V 80 80 pFIL(5, 14)TIMING CHARACTERISTICSData Setup Time t T = Full Temperature Range 40 40 nsDS AData Hold Time t T = Full Temperature Range 80 80 nsDH AClock Pulse Width High t T = Full Temperature Range 90 90 nsCH AClock Pulse Width Low t T = Full Temperature Range 120 120 nsCL ALoad Pulse Width t T = Full Temperature Range 120 120 nsLD ALSB Clock into Input Registerto Load DAC Register Time t T = Full Temperature Range 0 0 nsASB APOWER SUPPLYSupply Voltage V 4.75 5 5.25 4.75 5 5.25 VDDSupply Current I Digital Inputs = V or V 500 500 μADD IH ILDigital Inputs = 0V or V 100 100 μADDNOTES: (1) ±1/2 LSB = ±0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to I ; AllOUTdigital inputs = 0V. (5) Guaranteed by design and not tested. (6) I Load = 100Ω, C = 13pF, digital input = 0V to V or V to 0V. Extrapolated to 1/2 LSB:OUT EXT DD DDt = propagation delay (t ) + 9τ where τ = measured time constant of the final RC decay. (7) V = +10V, all digital inputs = 0V. (8) Absolute temperature coefficientS PD REFis less than ±50ppm/°C. (9) Digital inputs are CMOS gates: I is typically 1nA at +25°C. (10) V = 0V, all digital inputs = 0V to V or V to 0V. (11) All digitalIN REF DD DDinputs = 0V. (12) Calculated from worst case R : I (in LSBs) = (R X I X 4096)/V . (13) Calculations from en = √4K TRB where: K = Boltzmann constant,REF ZSE REF LKG REFJ/°K, R = resistance, Ω. T = Resistor temperature, °K, B = bandwidth, Hz. (14) Tested at V = 0V or V .IN DDThe information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.®2DAC8043WAFER TEST LIMITSAt V = +5V; V = +10V; I = GND = 0V; T = +25°C.DD REF OUT ADAC8043PARAMETER SYMBOL CONDITIONS LIMIT UNITSSTATIC ACCURACYResolution N 12 Bits minIntegral Nonlinearity INL ±1 LSB maxDifferential Nonlinearity DNL ±1 LSB maxGain Error G Using Internal Feedback Resistor ±2 LSB maxFSEPower Supply Rejection Ratio PSRR ΔV = ±5% ±0.002 %/% maxDDOutput Leakage Current (I)I Digital Inputs = V ±5 nA maxOUT LKG ILREFERENCE INPUTInput Resistance R 7/15 kΩ min/maxINDIGITAL INPUTSDigital Input HIGH V 2.4 V minIHDigital Input LOW V 0.8 V maxILInput Leakage Current I V = 0V to V ±1 μA maxIL IN DDPOWER SUPPLYSupply Current I Digital Inputs = V or V 500 μA maxDD IH ILDigital Inputs = 0V to V 100 μA maxDDNOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is notguaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.ABSOLUTE FEATURESAPPLICATIONSl 12-BIT ACCURACY IN 8-PIN SOICl AUTOMATIC CALIBRATIONl FAST 3-WIRE SERIAL INTERFACEl MOTION CONTROLl LOW INL AND DNL: ±1/2 LSB maxl MICROPROCESSOR CONTROL SYSTEMSl GAIN ACCURACY TO ±1LSB maxl PROGRAMMABLE AMPLIFIER/ATTENUATORSl LOW GAIN TEMPCO: 5ppm/°C maxl DIGITALLY CONTROLLED FILTERSl OPERATES WITH +5V SUPPLYl TTL/CMOS COMPATIBLEl ESD PROTECTEDDESCRIPTIONThe DAC8043 is a 12-bit current output multiplyingdigital-to-analog converter (DAC) that is packaged in aspace-saving, surface-mount 8-pin SOIC. Its 3-wire se-rial interface saves additional circuit board space whichRFB2results in low power dissipation. When used with micro-RFB12-Bitprocessors having a serial port, the DAC8043 minimizes13V IREF D/AOUTthe digital noise feedthrough from its input to output.ConverterThe serial port can be used as a dedicated analog bus andkept inactive while the DAC8043 is in use. Serial inter-12facing reduces the complexity of opto or transformerisolation applications.512-BitLDThe DAC8043 contains a 12-bit serial-in, parallel-out DAC Registershift register, a 12-bit DAC register, a 12-bit CMOS8VDAC, and control logic. Serial input (SRI) data is clockedDD12into the input register on the rising edge of the clock4GND7(CLK) pulse. When the new data word had been clockedCLK12-Bit Inputin, it is loaded into the DAC register by taking the LD6Shift RegisterSRIinput low. Data in the DAC register is converted to anoutput current by the D/A converter.The DAC8043 operates from a single +5V power supplywhich makes the DAC8043 an ideal low power, smallsize, high performance solution for several applications.International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132®1993 Burr-Brown Corporation PDS-1197B Printed in U.S.A. March, 19981DAC8043SBAS028SPECIFICATIONSMaximum Ratings, unless otherwise noted.DD REF OUT A DAC8043U DAC8043UCPARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITSSTATIC PERFORMANCEResolution N 12 12 Bits(1)Nonlinearity INL ±1 ±1/2 LSB(2)Differential Nonlinearity DNL ±1 ±1/2 LSB(3)Gain Error FSE T = +25°C ±2 ±1 LSBAT = Full Temp Range ±2 ±2 LSBA(5)Gain Tempco TC ±5 ±5 ppm/°CFSEPower Supply Rejection Ratio PSRR ΔV = ±5% ±0.0006 ±0.002 ±0.0006 ±0.002 %/%DD(4)Output Leakage Current I T = +25°C ±5 ±5nALKG AT = Full Temp Range ±100 ±25 nAA(7, 12)Zero Scale Error I T = +25°C 0.03 0.03 LSBZSE AT = Full Temp Range 0.60 0.15 LSBA(8)Input Resistance R 7 11 15 7 11 15 kΩINAC PERFORMANCE(5, 6)Output Current Settling Time t T = +25°C 0.25 1 0.25 1 μsS ADigital-to-Analog Glitch V = 0V 2 20 2 20 nVsREF(5, 10)Energy QI = Load = 100ΩOUTC = 13pFEXTDAC Register Loaded Alternately with all 0s and all 1s(5, 11)Feedthrough Error FT V = 20Vp-p at f = 10kHz 0.7 1 0.7 1 mVp-pREF (V to I ) Digital Input = 0000 0000 0000REF OUTT = +25°CA(5)Total Harmonic Distortion THD V = 6V at 1kHz –85 –85 dBREF RMSDAC Register Loaded with all 1s(5, 13)Output Noise Voltage Density e 10Hz to 100kHz 17 17 nV/√HzNBetween R and IFB OUTDIGITAL INPUTSDigital Input High V 2.4 2.4 VIHDigital Input Low V 0.8 0.8 VIL(9)Input Leakage Current I V = 0V to +5V ±1 ±1 μAIL IN(5, 11)Input Capacitance C V = 0V 8 8 pFIN INANALOG OUTPUTS(5)Output Capacitance C Digital Inputs = V 110 110 pFOUT IHDigital Inputs = V 80 80 pFIL(5, 14)TIMING CHARACTERISTICSData Setup Time t T = Full Temperature Range 40 40 nsDS AData Hold Time t T = Full Temperature Range 80 80 nsDH AClock Pulse Width High t T = Full Temperature Range 90 90 nsCH AClock Pulse Width Low t T = Full Temperature Range 120 120 nsCL ALoad Pulse Width t T = Full Temperature Range 120 120 nsLD ALSB Clock into Input Registerto Load DAC Register Time t T = Full Temperature Range 0 0 nsASB APOWER SUPPLYSupply Voltage V 4.75 5 5.25 4.75 5 5.25 VDDSupply Current I Digital Inputs = V or V 500 500 μADD IH ILDigital Inputs = 0V or V 100 100 μADDNOTES: (1) ±1/2 LSB = ±0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to I ; AllOUTdigital inputs = 0V. (5) Guaranteed by design and not tested. (6) I Load = 100Ω, C = 13pF, digital input = 0V to V or V to 0V. Extrapolated to 1/2 LSB:OUT EXT DD DDt = propagation delay (t ) + 9τ where τ = measured time constant of the final RC decay. (7) V = +10V, all digital inputs = 0V. (8) Absolute temperature coefficientS PD REFis less than ±50ppm/°C. (9) Digital inputs are CMOS gates: I is typically 1nA at +25°C. (10) V = 0V, all digital inputs = 0V to V or V to 0V. (11) All digitalIN REF DD DDinputs = 0V. (12) Calculated from worst case R : I (in LSBs) = (R X I X 4096)/V . (13) Calculations from en = √4K TRB where: K = Boltzmann constant,REF ZSE REF LKG REFJ/°K, R = resistance, Ω. T = Resistor temperature, °K, B = bandwidth, Hz. (14) Tested at V = 0V or V .IN DDThe information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.®2DAC8043WAFER TEST LIMITSAt V = +5V; V = +10V; I = GND = 0V; T = +25°C.DD REF OUT ADAC8043PARAMETER SYMBOL CONDITIONS LIMIT UNITSSTATIC ACCURACYResolution N 12 Bits minIntegral Nonlinearity INL ±1 LSB maxDifferential Nonlinearity DNL ±1 LSB maxGain Error G Using Internal Feedback Resistor ±2 LSB maxFSEPower Supply Rejection Ratio PSRR ΔV = ±5% ±0.002 %/% maxDDOutput Leakage Current (I)I Digital Inputs = V ±5 nA maxOUT LKG ILREFERENCE INPUTInput Resistance R 7/15 kΩ min/maxINDIGITAL INPUTSDigital Input HIGH V 2.4 V minIHDigital Input LOW V 0.8 V maxILInput Leakage Current I V = 0V to V ±1 μA maxIL IN DDPOWER SUPPLYSupply Current I Digital Inputs = V or V 500 μA maxDD IH ILDigital Inputs = 0V to V 100 μA maxDDNOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is notguaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.ABSOLUTE

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