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BUK9606-55A |BUK960655APHN/a487avaiN-channel TrenchMOS logic level FET


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BUK9606-55A
N-channel TrenchMOS logic level FET
BUK9606-55A
N-channel TrenchMOS logic level FET
Rev. 04 — 31 May 2010 Product data sheet Product profile
1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance Q101 compliant Suitable for logic level gate drive
sources Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads Automotive and general purpose
power switching Motors, lamps and solenoids
NXP Semiconductors BUK9606-55A
N-channel TrenchMOS logic level FET
1.4 Quick reference data

[1] Continuous current is limited by package. Pinning information Ordering information
Table 1. Quick reference data

VDS drain-source
voltage≥25 °C; Tj≤ 175°C --55 V drain current VGS =5V; Tj =25°C;
see Figure 3; see Figure 1
[1] --75 A
Ptot total power
dissipation
Tmb=25 °C; see Figure 2 --300 W
Static characteristics

RDSon drain-source
on-state
resistance
VGS =10V; ID =25A; =25°C
-4.8 5.8 mΩ
VGS =4.5 V; ID =25A; =25°C
--6.7 mΩ
VGS =5V; ID =25A; =25°C;
see Figure 12; see Figure 13
-5.3 6.3 mΩ
Avalanche ruggedness

EDS(AL)S non-repetitive
drain-source
avalanche energy =75A; Vsup≤55V;
RGS =50 Ω; VGS =5V;
Tj(init)=25 °C; unclamped
--1.1 J
Table 2. Pinning information
G gate
SOT404 (D2PAK)
D drain source D mounting base; connected to
drain
Table 3. Ordering information

BUK9606-55A D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads
(one lead cropped)
SOT404
NXP Semiconductors BUK9606-55A
N-channel TrenchMOS logic level FET Limiting values

[1] Current is limited by power dissipation chip rating.
[2] Continuous current is limited by package.
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C --55 V
VDGR drain-gate voltage RGS =20kΩ --55 V
VGS gate-source voltage -15 - 15 V drain current VGS =5V; Tj =25 °C;
see Figure 3; see Figure 1
[1] - - 154 A
[2] --75 A
VGS =5V; Tj= 100 °C; see Figure 1 [2] --75 A
IDM peak drain current Tmb =25°C; tp≤10 µs; pulsed;
see Figure 3 - 616 A
Ptot total power dissipation Tmb =25°C; see Figure 2 - - 300 W
Tstg storage temperature -55 - 175 °C junction temperature -55 - 175 °C
Source-drain diode
source current Tmb =25°C [1] - - 154 A
[2] --75 A
ISM peak source current tp≤10 µs; pulsed; Tmb=25°C - - 616 A
Avalanche ruggedness

EDS(AL)S non-repetitive
drain-source
avalanche energy =75A; Vsup≤55 V; RGS =50Ω;
VGS =5V; Tj(init)=25 °C; unclamped
--1.1 J
NXP Semiconductors BUK9606-55A
N-channel TrenchMOS logic level FET

NXP Semiconductors BUK9606-55A
N-channel TrenchMOS logic level FET Thermal characteristics

Table 5. Thermal characteristics

Rth(j-mb) thermal resistance
from junction to
mounting base
see Figure 4 --0.5 K/W
Rth(j-a) thermal resistance
from junction to
ambient
mounted on a printed-circuit board;
minimum footprint
-50 - K/W
NXP Semiconductors BUK9606-55A
N-channel TrenchMOS logic level FET Characteristics

Table 6. Characteristics
Static characteristics

V(BR)DSS drain-source
breakdown voltage =0.25mA; VGS =0V; Tj=25°C 55 --V =0.25mA; VGS =0V; Tj= -55°C 50 - - V
VGS(th) gate-source threshold
voltage =1mA; VDS =VGS; Tj =25°C;
see Figure 11
11.5 2V =1mA; VDS =VGS; Tj =-55 °C;
see Figure 11
--2.3 V =1mA; VDS =VGS; Tj= 175 °C;
see Figure 11
0.5 --V
IDSS drain leakage current VDS =55V; VGS =0V; Tj= 175°C - - 500 µA
VDS =55V; VGS =0V; Tj=25°C - 0.05 10 µA
IGSS gate leakage current VDS =0V; VGS =10V; Tj=25°C - 2 100 nA
VDS =0V; VGS =-10 V; Tj=25°C - 2 100 nA
RDSon drain-source on-state
resistance
VGS =5V; ID =25A; Tj= 175 °C;
see Figure 12; see Figure 13 - 13.2 mΩ
VGS =10V; ID =25A; Tj =25°C - 4.8 5.8 mΩ
VGS =4.5 V; ID =25A; Tj=25°C --6.7 mΩ
VGS =5V; ID =25A; Tj =25 °C;
see Figure 12; see Figure 13
-5.3 6.3 mΩ
Dynamic characteristics

Ciss input capacitance VGS =0V; VDS =25V; f=1MHz; =25°C; see Figure 14 6500 8600 pF
Coss output capacitance - 1000 1200 pF
Crss reverse transfer
capacitance 650 850 pF
td(on) turn-on delay time VDS =30V; RL =1.2 Ω; VGS =5V;
RG(ext) =10 Ω; Tj =25°C
-45 - ns rise time - 180 - ns
td(off) turn-off delay time - 420 - ns fall time - 235 - ns internal drain
inductance
from drain lead 6 mm from package to
centre of die ; Tj =25°C
-4.5 -nH
from upper edge of drain mounting base
to centre of die ; Tj =25°C
-2.5 -nH internal source
inductance
from source lead to source bond pad; =25°C
-7.5 -nH
Source-drain diode

VSD source-drain voltage IS =30A; VGS =0V; Tj =25°C;
see Figure 15 0.85 1.2 V
trr reverse recovery time IS =20A; dIS/dt= -100 A/µs;
VGS =-10 V; VDS =30 V; Tj =25°C
-80 - ns recovered charge - 200 - nC
NXP Semiconductors BUK9606-55A
N-channel TrenchMOS logic level FET
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