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BUK7624-55 |BUK762455PHILIPSN/a750avaiTrenchMOS transistor Standard level FET


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BUK7624-55
TrenchMOS transistor Standard level FET
Philips Semiconductors Product specification
TrenchMOS transistor BUK7624-55
Standard level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope VDS Drain-source voltage 55 V
suitablefor surface mounting. Using ID Drain current (DC) 45 A
’trench’ technology the device Ptot Total power dissipation 103 W
featuresvery low on-state resistance Tj Junction temperature 175 ˚C
and has integral zener diodes giving RDS(ON) Drain-source on-state 24 mΩ
ESD protection up to 2kV.It is resistance VGS = 10 V
intended for usein automotive and
general purpose switching
applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
gate drain source drain
LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ -55 V
±VGS Gate-source voltage - - 16 V Drain current (DC) Tmb = 25 ˚C - 45 A Drain current (DC) Tmb = 100 ˚C - 31 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 180 A
Ptot Total power dissipation Tmb = 25 ˚C - 103 W
Tstg, Tj Storage & operating temperature - - 55 175 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Rth j-mb Thermal resistance junction to - - 1.45 K/W
mounting base13
Philips Semiconductors Product specification
TrenchMOS transistor BUK7624-55
Standard level FET
STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 175˚C 1.0 - - V
Tj = -55˚C - - 4.4
IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 μA
Tj = 175˚C - - 500 μA
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 1 μA
Tj = 175˚C - - 20 μA
±V(BR)GSS Gate source breakdown voltage IG = ±1 mA; 16 - - V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 25 A - 19 24 mΩ
resistance Tj = 175˚C - - 50 mΩ
DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
fs Forward transconductance VDS = 25 V; ID = 25 A 4 11 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1100 1500 pF
Coss Output capacitance - 280 340 pF
Crss Feedback capacitance - 130 180 pF
td on Turn-on delay time VDD = 30 V; ID = 25 A; - 12 18 ns Turn-on rise time VGS = 10 V; RG = 10 Ω - 1935ns
td off Turn-off delay time Resistive load - 25 35 ns Turn-off fall time - 18 25 ns Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die Internal source inductance Measured from source lead - 7.5 - nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

IDR Continuous reverse drain - - 45 A
current
IDRM Pulsed reverse drain current - - 160 A
VSD Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 40 A; VGS = 0 V - 1.0 -
trr Reverse recovery time IF = 40 A; -dIF/dt = 100 A/μs; - 40 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.07 - μC
Philips Semiconductors Product specification
TrenchMOS transistor BUK7624-55
Standard level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

WDSS Drain-source non-repetitive ID = 40 A; VDD ≤ 25 V; - - 80 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T 20 40 60 80 100 120 140 160 180
Tmb / C
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10 10 100 10001
VDS / V
ID / A
RDS(ON) = VDS / ID 20 40 60 80 100 120 140 160 180
Tmb / C
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10 10us 1ms 0.1s 10s
pulse width, tp (s)
Transient thermal impedance, Zth (K/W)10
0.1
0.001
Philips Semiconductors Product specification
TrenchMOS transistor BUK7624-55
Standard level FET

Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.7. Typical transfer characteristics.
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
Fig.10. Gate threshold voltage. 2 468 100
ID/A
VSD/V 20 406080 1000
gfs/S
ID/A 1020 30405060708015 RDS(ON)/mOhm
ID/A
-100 -50 0 50 100 150 200
Tmb / degC
Rds(on) normlised to 25degCa
024 68 10 120
ID/A
VGS/V
-100 -50 0 50 100 150 2000
Tj / C
Philips Semiconductors Product specification
TrenchMOS transistor BUK7624-55
Standard level FET

Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
Fig.16. Avalanche energy test circuit. 23 451E-06
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction 0.5 1 1.50
IF/A
VSDS/V
0.01 0.1 1 10 100
Thousands pF
VDS/V 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
WDSS% 5 10 15 20 25 30 350
VGS/V
QG/nC
T.U.T.
VDD
VGS=0.5 ⋅LI⋅BV /(BV −V)
Philips Semiconductors Product specification
TrenchMOS transistor BUK7624-55
Standard level FET

Fig.17. Switching test circuit.
VDDVGS
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