BUH515 ,Silicon NPN Power Transistors TO-3PML packageBUH515®HIGH VOLTAGE FAST-SWITCHINGNPN POWER TRANSISTOR■ HIGH VOLTAGE CAPABILITY ■ FULLY INSULATED P ..
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BUH517
CRT HORIZONTAL DEFLECTION
HIGH VO ..
BUH517 ,Silicon NPN Power Transistors TO-3PML packageABSOLUTE MAXIMUM RATINGS
ISOWATT218
SC05310
INTERNAL SCHEMATIC DIAGRAM
Symbol Parameter ..
BUJ100 ,NPN power transistor
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BUH515
Silicon NPN Power Transistors TO-3PML package
BUH515HIGH VOLTAGE FAST-SWITCHING
NPN POWER TRANSISTOR HIGH VOLTAGE CAPABILITY FULLY INSULATED PACKAGE (U.L.
COMPLIANT) FOR EASY MOUNTING
APPLICATIONS: HORIZONTAL DEFLECTION FOR COLOUR
TVS AND MONITORS SWITCH MODE POWER SUPPLIES
DESCRIPTION The BUH515 is manufactured using Multiepitaxial
Mesa technology for cost-effective high
performance and uses a Hollow Emitter structure
to enhance switching speeds.
The BUH series is designed for use in horizontal
deflection circuits in televisions and monitors.
July 2002
ABSOLUTE MAXIMUM RATINGS1/7
THERMAL DATA
ELECTRICAL CHARACTERISTICS (Tcase = 25 o C unless otherwise specified)
∗ Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %
Safe Operating Area Thermal Impedance
BUH5152/7
Derating Curve
Collector Emitter Saturation Voltage
Power Losses at 16 KHz
DC Current Gain
Base Emitter Saturation Voltage
Switching Time Inductive Load at 16KHz
(see figure 2)
BUH5153/7
Power Losses at 32 KHz Switching Time Inductive Load at 32 KHz
(see figure 2)
In order to saturate the power switch and reduce
conduction losses, adequate direct base current
IB1 has to be provided for the lowest gain hFE at
100 oC (line scan phase). On the other hand,
negative base current IB2 must be provided to
turn off the power transistor (retrace phase).
Most of the dissipation, in the deflection
application, occurs at switch-off. Therefore it is
essential to determine the value of IB2 which
minimizes power losses, fall time tf and,
consequently, Tj. A new set of curves have been
defined to give total power losses, ts and tf as a
function of IB2 at both 16 KHz and 32 KHz
scanning frequencies for choosing the optimum
negative drive. The test circuit is illustrated in
figure 1.
Inductance L1 serves to control the slope of the
negative base current IB2 to recombine the
excess carrier in the collector when base current
is still present, this would avoid any tailing
phenomenon in the collector current.
The values of L and C are calculated from the
following equations: L (IC)2 = 1 C (VCEfly)2 ω = 2 πf = 1L C
Where IC= operating collector current, VCEfly=
flyback voltage, f= frequency of oscillation during
retrace.
BASE DRIVE INFORMATIONReverse Biased SOA Switching Time Resistive Load
BUH5154/7
Figure 1: Inductive Load Switching Test Circuit.
Figure 2: Switching Waveforms in a Deflection Circuit
BUH5155/7
BUH5156/7
