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ATF2500C-20JI from ATMEL, Atmel 273pcs , PLCC , Alternate PN:ATF2500C20JI,ATF2500C CPLD Family Datasheet
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ATF2500C-20JI ATMEL N/a 273
Block DiagramPLCC/LCC/JLCCDIPPin ConfigurationsCLK/IN 1 40 ININ 2 39 INPin Name FunctionIN 3 38 INI/O0 4 37 ININ Logic Inputs I/O1 5 36 I/O6I/O2 6 35 I/O7 I/O2 7 39 I/O7I/O3 7 34 I/O8I/O3 8 38 I/O8CLK/IN Pin Clock and InputI/O4 8 33 I/O9I/O4 9 37 I/O9I/O5 9 32 I/O10I/O5 10 36 I/O10VCC 10 31 I/O11I/O Bi-directional BuffersVCC 11 35 I/O11I/O17 11 30 GNDI/O16 12 29 I/O23VCC 12 34 GNDI/O15 13 28 I/O22I/O 0,2,4... “Even” I/O Buffers I/O17 13 33 GNDI/O14 14 27 I/O21I/O16 14 32 I/O23I/O13 15 26 I/O20I/O15 15 31 I/O22I/O12 16 25 I/O19I/O 1,3,5... “Odd” I/O BuffersIN 17 24 I/O18 I/O14 16 30 I/O21IN 18 23 INI/O13 17 29 I/O20GND GroundIN 19 22 ININ 20 21 INVCC +5V SupplyNote: (PLCC/LCC/JLCC packages) pin 4 and pin 26GND connections are not required, but are rec-Rev. 0777I–PLD–4/03ommended for improved noise immunity.1I/O12 18 6 I/O15IN 19 I/O0IN 20 4 GNDIN 21 3 ININ 22 2 ININ 23 1 CLK/IN44IN 24 ININ 25 43 INGND 26 42 INI/O18 27 41 INI/O19 28 40 I/O6Description The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully con-nected logic array and flexible macrocell structure, high gate utilization is easily obtainable.The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logicdevice (PLD) that utilizes Atmel’s proven electrically-erasable technology.The ATF2500C is organized around a single universal array. All pins and feedback terms arealways available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-puts of each flip-flop.In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-cell’s three sum terms can be combined to provide up to 12 product terms per sum term withno performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internalcombinatorial feedback to the logic array.Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has itsown enable product term. Eight synchronous preset product terms serve local groups of eitherfour or eight flip-flops. Register preload functions are provided to simplify testing. All registersautomatically reset upon power-up.Using the The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.Some of the ATF2500Cs key

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