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ADV7322KSTZ
Multiformat 11-Bit HDTV Video Encoder
Multiformat 11-Bit
HDTV Video Encoder
Rev. PrA
FEATURES
High definition input formats
16-, 24-bit (4:2:2, 4:4:4) parallel YCrCb
Fully compliant with
SMPTE 274M (1080i, 1080p @ 74.25 MHz)
SMPTE 296M (720p)
SMPTE 240M (1035i)
RGB in 3- × 8-bit 4:4:4 input format
HDTV RGB supported
RGB, RGBHV
Other high definition formats using async
timing mode
Enhanced definition input formats
8-, 16-, 24-bit (4:2:2, 4:4:4) parallel YCrCb
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
RGB in 3- × 8-bit 4:4:4 input format
Standard definition input formats
CCIR-656 4:2:2 8-bit or 16-bit parallel input
High definition output formats
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Enhanced definition output formats
Macrovision Rev 1.2 (525p/625p)
CGMS-A (525p/625p)
YPrPb progressive scan (EIA-770.1, EIA-770.2)
RGB, RGBHV
Standard definition output formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC-compatible composite video
ITU-R BT.470 PAL-compatible composite video
S-video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed captioning
GENERAL FEATURES
Simultaneous SD/HD, PS/SD inputs and outputs
Oversampling up to 216 MHz
Programmable DAC gain control
Sync outputs in all modes
On-board voltage reference
Six 11-bit precision video DACs
2-wire serial I2C® interface, open-drain configuration
Dual I/O supply 2.5 V/3.3 V operation
Analog and digital supply 2.5 V
On-board PLL
64-lead LQFP package
Lead (Pb)-free product
APPLICATIONS
EVD players (enhanced versatile disk)
SD/PS DVD recorders/players
SD/progressive scan/HDTV display devices
SD/HDTV set top boxes
CLKIN_A
CLKIN_B
HSYNC
VSYNC
BLANK
Y7–Y0C7–C0S7–S0 Figure 1. Simplified Functional Block Diagram
GENERAL DESCRIPTION The ADV®7322 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes six high speed video DACs
with TTL compatible inputs. It has separate 8-, 16-, 24-bit input
ports that accept data in high definition and/or standard
definition video format. For all standards, external horizontal,
vertical, and blanking signals or EAV/SAV timing codes control
the insertion of appropriate synchronization signals into the
digital data stream and therefore the output signal.
TABLE OF CONTENTS Specifications.....................................................................................6
Dynamic Specifications...................................................................7
Timing Specifications.......................................................................8
Timing Diagrams..............................................................................9
Absolute Maximum Ratings..........................................................17
Thermal Characteristics............................................................17
Pin Configuration and Function Descriptions...........................18
Typical Performance Characteristics...........................................20
MPU Port Description...................................................................24
Register Access................................................................................26
Register Programming...............................................................26
Subaddress Register (SR7 to SR0)............................................26
Input Configuration.......................................................................39
Standard Definition Only..........................................................39
Progressive Scan Only or HDTV Only...................................39
Simultaneous Standard Definition and Progressive Scan or
HDTV..........................................................................................39
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz...........40
Features............................................................................................42
Output Configuration................................................................42
HD Async Timing Mode...........................................................43
HD Timing Reset........................................................................44
SD Real-Time Control, Subcarrier Reset, and Timing Reset44
Reset Sequence............................................................................46
SD VCR FF/RW Sync.................................................................46
Vertical Blanking Interval.........................................................47
Subcarrier Frequency Registers................................................47
Square Pixel Timing Mode........................................................48
Filters............................................................................................49
Color Controls and RGB Matrix..............................................50
Programmable DAC Gain Control..........................................54
HD Sharpness Filter and Adaptive Filter Controls................56
HD Sharpness Filter and Adaptive Filter Application
Examples......................................................................................57
SD Digital Noise Reduction......................................................58
Coring Gain Border...................................................................59
Coring Gain Data.......................................................................59
DNR Threshold..........................................................................59
Border Area.................................................................................59
Block Size Control......................................................................59
DNR Input Select Control.........................................................59
DNR Mode Control...................................................................60
Block Offset Control..................................................................60
SD Active Video Edge................................................................60
SAV/EAV Step Edge Control....................................................60
Board Design and Layout..............................................................62
DAC Termination and Layout Considerations......................62
Video Output Buffer and Optional Output Filter..................62
PCB Board Layout......................................................................63
Appendix 1—Copy Generation Management System..............65
PS CGMS.....................................................................................65
HD CGMS...................................................................................65
SD CGMS....................................................................................65
Function of CGMS Bits.............................................................65
CGMS Functionality..................................................................65
Appendix 2—SD Wide Screen Signaling.....................................68
Appendix 3—SD Closed Captioning...........................................69
Appendix 4—Test Patterns............................................................70
Appendix 5—SD Timing Modes..................................................73
Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 =
X X X X X 0 0 0).........................................................................73
Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0
Mode 1—Slave Option (Timing Register 0 TR0 = X X X X X
0 1 0).............................................................................................76
Mode 1—Master Option (Timing Register 0 TR0 = X X X X
X 0 1 1)..........................................................................................77
Mode 2— Slave Option (Timing Register 0 TR0 = X X X X X
1 0 0).............................................................................................78
Mode 2—Master Option (Timing Register 0 TR0 = X X X X
X 1 0 1)..........................................................................................79
Mode 3—Master/Slave Option (Timing Register 0 TR0 = X
X X X X 1 1 0 or X X X X X 1 1 1)...........................................80
Appendix 6—HD Timing..............................................................81
Appendix 7—Video Output Levels...............................................82
HD YPrPb Output Levels...........................................................82
RGB Output Levels.....................................................................83
YPrPb Levels—SMPTE/EBU N10............................................84
Appendix 8—Video Standards......................................................86
Outline Dimensions........................................................................88
Ordering Guide...........................................................................88
REVISION HISTORY
9/04—PrA: Preliminary Version DETAILED FEATURES
High definition programmable features (720p/1080i/1035i)
2× oversampling (148.5 MHz)
Internal test pattern generator
Color hatch, black bar, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS-A (720p/1080i)
Enhanced definition programmable features (525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Color hatch, black bar, flat frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p)
CGMS-A (525p/625p)
Standard definition programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color bars, black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF™ filter with programmable gain/attenuation
PrPb SSAF™
Separate pedestal control on component and
composite/S-video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1
CGMS/WSS
Closed captioning
Table 1. Standards Directly Supported1 Other standards are supported in async timing mode.
CLKIN_A
CLKIN_B
HD PIXELINPUT
SD PIXELINPUTFigure 2. Detailed Functional Block Diagram
TERMINOLOGY SD: standard definition video, conforming to
ITU-R BT.601/ITU-R BT.656.
HD: high definition video, i.e., 720p/1080i/1035i.
EDTV: enhanced definition television (525p/625p)
PS: progressive scan video, conforming to SMPTE 293M,
ITU-R BT.1358, BTAT-1004EDTV2, or ITU-R BT.13621362.
HDTV: high definition television video, conforming to SMPTE
274M, or SMPTE 296M and SMPTE240M.
YCrCb SD, PS, or HD component: digital video.
YPrPb SD, PS, or HD component: analog video.
