ADV7197KS Fast Delivery |IC PHOENIX CO.,LIMITED

ADV7197KS ,Multiformat HDTV Encoder with Three 11-Bit DACsGENERAL DESCRIPTIONcodes control the insertion of appropriate synchronization signalsThe ADV7197 is ..
ADV7300AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACsFEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAMHigh Definition Input FormatsYCrCb Compliant to SMPTE29 ..
ADV7301AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACsSPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 760 , R = 150 , T t ..
ADV7302AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACsSPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 760 , R = 150 , T t ..
ADV7304AKST ,14-bit 108MHz Video Encoder with NSV™ and Macrovision® Copy ProtectionFeatures (525 p/625 p) Luma-SSAF™ Filter with Programmable Gain/4 Oversampling (108 MHz Output) At ..
ADV7305AKST ,14-bit 108MHz Video Encoder with NSV™SPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 1520 , R = 150 , T ..
AM27S03APC , 64-Bit Inverting-Output Bipolar RAM
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AM27S07APC , 64-Bit Inverting-Output Bipolar RAM
AM27S07DC , 64-Bit Inverting-Output Bipolar RAM
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ADV7197KS
Multiformat HDTV Encoder with Three 11-Bit DACs
REV.0
Multiformat HDTV Encoder with
Three 11-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
FEATURES
INPUT FORMATS
YCrCb in 2 � 10-Bit (4:2:2) or 3 � 10-Bit (4:4:4) Format
Compliant to SMPTE274M (1080i), SMPTE296M
(720p) and Any Other High-Definition Standard Using
Async Timing Mode
RGB in 3 � 10-Bit 4:4:4 Format
OUTPUT FORMATS
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (�)
Individual DAC On/Off Control
VBI Open Control2C Filter
2-Wire Serial MPU Interface
Single Supply 5 V/3.3 V Operation
52-Lead MQFP Package
APPLICATIONS
HDTV Display Devices
HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
*ADV is a registered trademark of Analog Devices, Inc.
GENERAL DESCRIPTION
The ADV7197 is a triple, high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
The ADV7197 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB, or 4:2:2 10-bit
YCrCb. This data is accepted in HDTV format at 74.25 MHz
or 74.1758 MHz. For any other high definition standard but
SMPTE274M or SMPTE296M, the Async Timing Mode can
be used to input data to the ADV7197. For all standards,
external horizontal, vertical, and blanking signals or EAV/SAV
codes control the insertion of appropriate synchronization signals
into the digital data stream and therefore the output signals.
The ADV7197 outputs analog YPrPb HDTV complying to
EIA-770.3, or RGB complying to RS-170/RS-343A.
The ADV7197 requires a single 5 V/3.3 V power supply, an
optional external 1.235 V reference, and a 74.25 MHz (or
74.1758 MHz) clock.
The ADV7197 is packaged in a 52-lead MQFP package.
ADV7197–SPECIFICATIONS
5 V SPECIFICATIONS1
NOTESGuaranteed by characterization.IDD or the circuit current is the continuous current required to drive the digital core.IAA is the total current required to supply all DACs including VREF circuitry.All DACs on.
Specifications subject to change without notice.
(VAA = 4.75 V to 5.25 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications TMIN to TMAX [0�C to
70�C] unless otherwise noted.)
ADV7197
3.3 V SPECIFICATIONS1
NOTES
1Guaranteed by characterization.
2IDD or the circuit current is the continuous current required to drive the digital core.
3IAA is the total current required to supply all DACs including VREF circuitry.
4All DACs on.
Specifications subject to change without notice.
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications TMIN to TMAX [0�C
to 70�C] unless otherwise noted.)
ADV7197–SPECIFICATIONS
5 V DYNAMIC–SPECIFICATIONS
Specifications subject to change without notice.
3.3 V DYNAMIC–SPECIFICATIONS
Specifications subject to change without notice.
5 V TIMING–SPECIFICATIONS
ANALOG OUTPUTS
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV
Specifications subject to change without notice.
(VAA = 4.75 V to 5.25 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications TMIN
to TMAX [0�C to 70�C] unless otherwise noted.)
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications
TMIN to TMAX [0�C to 70�C] unless otherwise noted.)
(VAA = 4.75 V to 5.25 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications TMIN
to TMAX [0�C to 70�C] unless otherwise noted.)
ADV7197
3.3 V TIMING–SPECIFICATIONS
ANALOG OUTPUTS
NOTESGuaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV
Specifications subject to change without notice.
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications
TMIN to TMAX [0�C to 70�C] unless otherwise noted.)
Figure 1.4:2:2 Input Data Format Timing Diagram
ADV7197
Figure 2.4:4:4 YCrCb Input Data Format Timing Diagram
Figure 3.4:4:4 RGB Input Data Format Timing Diagram
Figure 4.Input Timing Diagram
t4 t8
SDA
SCL
t5
Figure 5.MPU Port Timing Diagram
ADV7197
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7197 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150°C
Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . 225°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
PIN CONFIGURATION
Cr[0]Cr[1]Cr[2]Cr[3]Cr[4]Cr[5]Cr[6]Cr[7]Cr[8]Cr[9]
CLKIN
GND
GNDCb/Cr[0]Cb/Cr[1]Cb/Cr[2]Cb/Cr[3]Cb/Cr[4]Cb/Cr[5]Cb/Cr[6]Cb/Cr[7]Cb/Cr[8]Cb/Cr[9]ALSBRESET
VDD
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
Y[9]
VDD
GND
VREF
RSET
COMP
DAC B
VAA
DAC A
AGND
DAC C
SDA
SCL
HSYNC/SYNC
VSYNC/TSYNC
ORDERING GUIDE
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PIN FUNCTION DESCRIPTIONS
ADV7197
FUNCTIONAL DESCRIPTION
Digital Inputs
The digital inputs of the ADV7197 are TTL-compatible. 30-bit
YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel
data in 4:2:2 format is latched into the device on the rising edge
of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode.
It is recommended to input data in 4:2:2 mode to make use of
the Chroma SSAFs on the ADV7197. As can be seen in the
figures below, these filters have 0 dB passband response and
prevent signal components being folded back into the frequency
band. In 4:4:4 input mode, the video data is already interpo-
lated by an external input device and the chroma SSAFs of the
ADV7197 are bypassed.
Figure 6.SSAF Response to a 2.5 MHz Chroma Sweep
Using 4:2:2 Input Mode
Figure 7.Conventional Filter Response to a 2.5 MHz Chroma
Sweep Using 4:4:4 Input Mode
Control Signals
The ADV7197 accepts sync control signals accompanied by
valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and
blanking pulses (or EAV/SAV codes) control the insertion of
appropriate sync information into the output signals.
(EIA-770.3), RLOAD has a value of 300 Ω. For the outputs to con-
form to RS-170/RS-343A standards RSET must have a value
of 2820 Ω.
Internal Test Pattern Generator
The ADV7197 can generate a Cross-Hatch pattern (white lines
against a black background). Additionally, the ADV7197 can
output a uniform color pattern. The color of the lines or uni-
form field/frame can be programmed by the user.
Y/CrCb Delay
The Y output and the color component outputs can be delayed
wrt the falling edge of the horizontal sync signal by up to four
clock cycles.2C Filter
A selectable internal I2C filter allows significant noise reduction
on the I2C interface. For setting ALSB high, the input band-
width on the I2C lines is reduced and pulses of less than 50ns
are not passed to the I2C controller. Setting ALSB low allows
greater input bandwidth on the I2C lines.
MPU PORT DESCRIPTION
The ADV7197 support a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. Two inputs Serial
Data (SDA) and Serial Clock (SCL) carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7197 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 8. The LSB
sets either a read or write operation. Logic Level “1” corresponds
to a read operation while Logic Level “0” corresponds to a write
operation. A1 is set by setting the ALSB pin of the ADV7197 to
Logic Level “0” or Logic Level “1.” When ALSB is set to “0,”
there is greater input bandwidth on the I2C lines, which allows
high-speed data transfers on this bus. When ALSB is set to “1,”
there is reduced input bandwidth on the I2C lines, which means
that pulses of less than 50 ns will not pass into the I2C internal
controller. This mode is recommended for noisy systems.
Figure 8.Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi-
tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/W
bit). The bits are transferred from MSB down to LSB. The periph-
eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known
as an Acknowledge Bit. All other devices withdraw from the bus

Partno	Mfg	Dc	Qty	Available	Descript
ADV7197KS	AD	N/a	235	avai	Multiformat HDTV Encoder with Three 11-Bit DACs