ADV7196AKS ,Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and MacrovisionGENERAL DESCRIPTIONAnticopy algorithm in 525p mode.The ADV7196A is a triple high-speed, digital-to- ..
ADV7197KS ,Multiformat HDTV Encoder with Three 11-Bit DACsGENERAL DESCRIPTIONcodes control the insertion of appropriate synchronization signalsThe ADV7197 is ..
ADV7300AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACsFEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAMHigh Definition Input FormatsYCrCb Compliant to SMPTE29 ..
ADV7301AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACsSPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 760 , R = 150 , T t ..
ADV7302AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACsSPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 760 , R = 150 , T t ..
ADV7304AKST ,14-bit 108MHz Video Encoder with NSV™ and Macrovision® Copy ProtectionFeatures (525 p/625 p) Luma-SSAF™ Filter with Programmable Gain/4 Oversampling (108 MHz Output) At ..
AM27H010-45DC , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27H010-45DI , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27S03APC , 64-Bit Inverting-Output Bipolar RAM
AM27S03PC , 64-Bit Inverting-Output Bipolar RAM
AM27S07APC , 64-Bit Inverting-Output Bipolar RAM
AM27S07DC , 64-Bit Inverting-Output Bipolar RAM
ADV7196AKS
Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
REV.0
Multiformat Progressive Scan/HDTV
Encoder with Three 11-Bit DACs,
10-Bit Data Input, and Macrovision
FUNCTIONAL BLOCK DIAGRAM
FEATURES
INPUT FORMATS
YCrCb in 2 � 10-Bit (4:2:2) or 3 � 10-Bit (4:4:4) Format
Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p) and
Any Other High Definition Standard Using Async
Timing Mode
RGB in 3 � 10 Bit (4:4:4) Format
OUTPUT FORMATS
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit and Sync (DAC A)
11-Bit DACs (DAC B, DAC C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (�)
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2� Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter2C® Filter
VBI Open Control
Macrovision Rev. 1.0 (525p)
CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package
APPLICATIONS
Progressive Scan/HDTV Display Devices
DVD Players
MPEG 2 at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal ReconstructionI2C is a registered trademark of Philips Corporation.
GENERAL DESCRIPTIONThe ADV7196A is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
The ADV7196A has three separate 10-bit-wide input ports which
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE 293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can be
used to input data to the ADV7196A. For all standards, external
horizontal, vertical, and blanking signals or EAV/SAV codes control
the insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
The ADV7196A outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.
The ADV7196A requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.
In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used, allows
removal of ringing on the incoming Y data. The ADV7196A
supports CGMS-A data control generation and the Macrovision
Anticopy algorithm in 525p mode.
The ADV7196A is packaged in a 52-lead MQFP package.
ADV7196A
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . .1
3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 V DYNAMIC–SPECIFICATIONS . . . . . . . . . . . . . . . . . .4
3.3 V TIMING–SPECIFICATIONS . . . . . . . . . . . . . . . . . .5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .8
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . .10
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102C Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . .10
Y/CrCb Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
54 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PROGRAMMABLE SHARPNESS FILTER . . . . . . . . . . .10
PROGRAMMABLE ADAPTIVE FILTER CONTROL . .10
Input/Output Configuration . . . . . . . . . . . . . . . . . . . . . . .11
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . .11
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . .12
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . .13
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . .13
Register Select (SR6–SR0) . . . . . . . . . . . . . . . . . . . . . . . .13
PROGRESSIVE SCAN MODE . . . . . . . . . . . . . . . . . . . . .14
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .14
Output Standard Selection (MR00–MR01) . . . . . . . . . . .14
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . .14
Input Standard (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . .14
Reserved (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Macrovision (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .16
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . .16
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . .16
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . .16
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Undershoot Limiter (MR15–MR16) . . . . . . . . . . . . . . . .16
Sharpness Filter (MR17) . . . . . . . . . . . . . . . . . . . . . . . . .16
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .17
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . .17
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . .17
CGMS Enable (MR26) . . . . . . . . . . . . . . . . . . . . . . . . . .17
CGMS CRC (MR27) . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .18
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . .18
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . .18
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . .18
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . .18
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . .18
Interpolation (MR36) . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Reserved (MR37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .18
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .18
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . .18
Gamma Curve (MR54) . . . . . . . . . . . . . . . . . . . . . . . . . .19
Gamma Correction (MR55) . . . . . . . . . . . . . . . . . . . . . .19
Adaptive Mode Control (MR56) . . . . . . . . . . . . . . . . . . .19
Adaptive Filter Control (MR57) . . . . . . . . . . . . . . . . . . .19
COLOR Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CY (CY7–CY0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
COLOR CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CCR (CCR7–CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
COLOR CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CCB (CCB7–CCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MODE REGISTER 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
MR6 (MR67–MR60) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
MR6 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .20
MR67–MR60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
CGMS DATA REGISTERS 2–0 . . . . . . . . . . . . . . . . . . . .20
CGMS2 (CGMS27–CGMS20) . . . . . . . . . . . . . . . . . . . .20
CGMS1 (CGMS17–CGMS10) . . . . . . . . . . . . . . . . . . . .20
CGMS0 (CGMS07–CGMS00) . . . . . . . . . . . . . . . . . . . .20
FILTER GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
FG (FG7–FG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
FG BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .21
Filter Gain A (FG3–FG0) . . . . . . . . . . . . . . . . . . . . . . . .21
Filter Gain B (FG4–FG7) . . . . . . . . . . . . . . . . . . . . . . . .21
GAMMA CORRECTION REGISTERS 0–13 . . . . . . . . . .21
(GAMMA CORRECTION 0–13) . . . . . . . . . . . . . . . . . .21
SHARPNESS FILTER CONTROL AND
ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . .22
SHARPNESS FILTER MODE . . . . . . . . . . . . . . . . . . . . .22
ADAPTIVE FILTER MODE . . . . . . . . . . . . . . . . . . . . . . .22
ADAPTIVE FILTER GAIN 1 . . . . . . . . . . . . . . . . . . . . . .23
AFG1 (AFG1)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ADAPTIVE FILTER GAIN 2 . . . . . . . . . . . . . . . . . . . . . .23
AFG2 (AFG2)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ADAPTIVE FILTER GAIN 3 . . . . . . . . . . . . . . . . . . . . . .23
AFG3 (AFG3)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ADAPTIVE FILTER THRESHOLD A . . . . . . . . . . . . . . .23
AFTA (AFTA)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ADAPTIVE FILTER THRESHOLD B . . . . . . . . . . . . . . .23
AFTB (AFTB)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ADAPTIVE FILTER THRESHOLD C . . . . . . . . . . . . . . .23
AFTC (AFTC)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . .24
Sharpness Filter Application . . . . . . . . . . . . . . . . . . . . . .24
Adaptive Filter Control Application . . . . . . . . . . . . . . . . .25
HDTV MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
HEXMR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . .26
Output Standard Selection (MR00–MR01) . . . . . . . . . . .26
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . .26
Reserved (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Input Standard (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . .26
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .27
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . .27
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . .27
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . .27
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reserved (MR15–MR17) . . . . . . . . . . . . . . . . . . . . . . . . .27
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .28
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . .28
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . .28
Reserved (MR26–MR27) . . . . . . . . . . . . . . . . . . . . . . . . .28
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .28
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . .28
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . .28
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . .28
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . .28
Reserved (MR36–MR37) . . . . . . . . . . . . . . . . . . . . . . . . .28
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .29
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .29
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . .29
Reserved (MR54–MR57) . . . . . . . . . . . . . . . . . . . . . . . . .29
DAC TERMINATION AND LAYOUT
CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . .30
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . .31
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .31
Video Output Buffer and Optional Output Filter . . . . . . .31
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .36
ADV7196A–SPECIFICATIONS
3.3 V SPECIFICATIONSNOTESGuaranteed by characterization.IDD or the circuit current is the continuous current required to drive the digital core without IPLL.IAA is the total current required to supply all DACs including the VREF circuitry.All DACs on.
Specifications subject to change without notice.
(VAA = 3.15V to 3.45V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications TMIN to TMAX
(0�C to 70�C) unless otherwise noted.)
3 V DYNAMIC–SPECIFICATIONSSpecifications subject to change without notice.
(VAA = 3.15V to 3.45V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications
TMIN to TMAX (0�C to 70�C) unless otherwise noted.)
ADV7196A
3.3 V TIMING–SPECIFICATIONSNOTESGuaranteed by characterization.Output delay measured from 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.Data: Cb/Cr [9–0], Cr [9–0], Y [9:0]
Control: HSYNC/SYNC, VSYNC/TSYNC, DV
Specifications subject to change without notice.
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 �, RLOAD = 300 �. All specifications
TMIN to TMAX (0�C to 70�C) unless otherwise noted.)
ADV7196AFigure 1.4:4:4 RGB Input Data Format Timing Diagram
Figure 2.4:2:2 Input Data Format Timing Diagram
Figure 3.4:4:4 YCrCb Input Data Format Timing Diagram
Figure 4.Input Timing Diagram
Figure 5.MPU Port Timing Diagram
ADV7196A
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7196A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . 225°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
PIN CONFIGURATION
Cr[0]Cr[1]Cr[2]Cr[3]Cr[4]Cr[5]Cr[6]Cr[7]Cr[8]Cr[9]
CLKIN
GND
GNDCb/Cr[0]Cb/Cr[1]Cb/Cr[2]Cb/Cr[3]Cb/Cr[4]Cb/Cr[5]Cb/Cr[6]Cb/Cr[7]Cb/Cr[8]Cb/Cr[9]ALSBRESET
VDD
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
Y[9]
VDD
GND
VREF
RSET
COMP
DAC B
VAA
DAC A
AGND
DAC C
SDA
SCL
HSYNC/SYNC
VSYNC/TSYNC
ORDERING GUIDENOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PIN FUNCTION DESCRIPTIONS
ADV7196A
FUNCTIONAL DESCRIPTION
Digital InputsThe digital inputs of the ADV7196A are TTL compatible. 30-bit
YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel
data in 4:2:2 format is latched into the device on the rising edge
of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode.
It is also possible to input 3 × 10 bit RGB data in 4:4:4 to the
ADV7196A. It is recommended to input data in 4:2:2 mode to
make use of the Chroma SSAFs on the ADV7196A. As can be
seen in the figure below, this filter has a 0dB pass band response
and prevents signal components being folded back in to the fre-
quency band. In 4:4:4: input mode, the video data is already
interpolated by the external input device and the Chroma SSAFs
of the ADV7196A are bypassed.
Figure 6.ADV7196A SSAF Response to a 2.5MHz Chroma
Sweep Using 4:2:2 Input Mode
Figure 7.Conventional Filter Response to a 2.5MHz Chroma
Sweep Using 4:4:4 Input Mode
Control SignalsThe ADV7196A accepts sync control signals accompanied by
valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and
Analog OutputsThe analog Y signal is output on the 11-Bit + Sync DAC A,
the color component analog signals on the 11-Bit DACs B, C
conforming to EIA-770.1 or EIA-770.2 standards in PS mode
or EIA-770.3 in HDTV mode. RSET has a value of 2470Ω
(EIA-770.1, EIA-770.2, EIA-770.3), RLOAD has a value of 300 Ω.
For RGB outputs conforming to RS-170/RS-343A output standards
RSET must have a value of 2820 Ω.
2C FiltersA selectable internal I2C filter allows significant noise reduction
on the I2C interface. In setting ALSB high, the input bandwidth
on the I2C lines is reduced and pulses of less than 50ns are not
passed to the I2C controller. Setting ALSB low allows greater
input bandwidth on the I2C lines.
Undershoot LimiterA limiter can be applied to the Y data before it is applied to the DACs.
Available limit values are –1.5 IRE, –6 IRE, –11 IRE below blank-
ing. This functionality is available in Progressive Scan mode only.
Internal Test Pattern GeneratorThe ADV7196A can generate a cross-hatch pattern (white lines
against a black background). Additionally, the ADV7196A can
output a uniform color pattern. The color of the lines or uniform
field/frame can be programmed by the user.
Y/CrCb DelayThe Y output and the color component outputs can be delayed
wrt the falling edge of the horizontal sync signal by up to four
clock cycles.
Gamma CorrectionGamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if gamma
correction is enabled. Gamma correction allows the mapping of
the luma data to a user-defined function.
54 MHz OperationIn Progressive Scan mode, it is possible to operate the three out-
put DACs at 54 MHz or 27 MHz. The ADV7196A is supplied
with a 27 MHz clock synced with the incoming data. If required, a
second stage interpolation filter interpolates the data to 54 MHz
before it is applied to the three output DACs. The second stage
interpolation filter is controlled by MR36. After applying a
Reset it is recommended to toggle this bit. Before toggling this bit,
3Ehex must be written to address 09hex.
PROGRAMMABLE SHARPNESS FILTERSharpness Filter Mode is applicable to the Y data only in Progres-
sive Scan mode. The desired frequency response can be chosen
by the user in programming the correct value via the I2C. The
variation of frequency responses can be seen in the figures on the
following pages.
PROGRAMMABLE ADAPTIVE FILTER CONTROLIf the Adaptive Filter Mode is enabled (Progressive Scan mode only),
it is possible to compensate for large edge transitions on the
incoming Y data. Sensitivity and attenuation are all program-
mable over the I2C. For further information refer to Sharpness
Filter Control and Adaptive Filter Control section.
Input/Output ConfigurationTable I shows possible input/output configurations when using
the ADV7196A.
Table I.Figure 8.2× Interpolation Filter – Y-Channel
Figure 9.Interpolation Filter – CrCb Channels for 4:2:2
Input Data
Figure 10.Interpolation Filter – CrCb Channels for 4:4:4
Input Data
MPU PORT DESCRIPTIONThe ADV7196A support a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. Two inputs, Serial Data
(SDA) and Serial Clock (SCL), carry information between any
device connected to the bus. Each slave device is recognized by a
unique address. The ADV7196A has four possible slave addresses
for both read and write operations. These are unique addresses
for each device and illustrated in Figure 11. The LSB sets either
a read or write operation. Logic Level “1” corresponds to a read
operation while Logic Level “0” corresponds to a write opera-
tion. A1 is set by setting the ALSB pin of the ADV7196A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “0,” there is
greater input bandwidth on the I2C lines, which allows high-
speed data transfers on this bus. When ALSB is set to “1,” there
is reduced input bandwidth on the I2C lines, which means that
pulses of less than 50 ns will not pass into the I2C internal control-
ler. This mode is recommended for noisy systems.
Figure 11.Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi-
tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/W
bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
ADV7196AA Logic “0” on the LSB of the first byte means that the master will
write information to the peripheral. A Logic “1” on the LSB of
the first byte means that the master will read information from
the peripheral.
The ADV7196A acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses plus
the R/W bit. It interprets the first byte as the device address and
the second byte as the starting subaddress. The subaddresses auto-
increment allowing data to be written to or read from the starting
subaddress. A data transfer is always terminated by a Stop con-
dition. The user can also access any unique subaddress register
on a one by one basis without having to update all the registers.
Stop and Start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, then these cause an immedi-
ate jump to the idle condition. During a given SCL high period
the user should only issue one Start condition, one Stop condition
or a single Stop condition followed by a single Start condition.
If an invalid subaddress is issued by the user, the ADV7196A will
not issue an acknowledge and will return to the idle condition. If
in autoincrement mode, the user exceeds the highest subaddress
then the following action will be taken:In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the
ninth pulse.In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7196A and the part will return to the
idle condition.
Figure 12.Bus Data Transfer
Figure 12 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
Figure 13 shows bus write and read sequences.
REGISTER ACCESSESThe MPU can write to or read from all of the registers of the
ADV7196A except the Subaddress Registers, which are write-only
registers. The Subaddress Register determines which register the
next read or write operation accesses.
All communications with the part through the bus begin with an
access to the Subaddress Register. A read/write operation is per-
formed from/to the target address which then increments to the
next address until a Stop command on the bus is performed.
Figure 13.Write and Read Sequence
REGISTER PROGRAMMINGThe following section describes the functionality of each register.
All registers can be read from as well as written to unless other-
wise stated.
Subaddress Register (SR7–SR0)The Communications Register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation takes place.
Figure 14 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.
Register Select (SR6–SR0)These bits are set up to point to the required starting address.
Figure 14.Subaddress Registers in Progressive Scan Mode
ADV7196A
PROGRESSIVE SCAN MODE
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)Figure 16 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)These bits are used to select the output levels for the ADV7196A.
If EIA-770.2 (MR01–00 = “00”) is selected the output levels will
be: 0 mV for blanking level, 700 mV for peak white for the Y
channel, ±350 mV for Pr, Pb outputs and –300 mV for Sync. Sync
insertion on the Pr, Pb channels is optional.
If EIA-770.1 (MR01–00 = “01”) is selected the output levels will
be: 0 mV for blanking level, 714 mV for peak white for the Y chan-
nel, ±350 mV for Pr, Pb outputs and –286 mV for Sync. Optional
sync insertion on the Pr, Pb channels is not possible.
If Full I/P Range (MR01–00 = “10”) is selected the output levels
will be 0 mV for blanking level, 700 mV for peak white for the Y
channel, ±350 mV for Pr, Pb outputs and –300 mV for Sync. Sync
insertion on the Pr, Pb channels is optional. This mode is used
for RS-170, RS-343A standard output compatibility. Refer to
Appendix for output level plots.
Input Control Signals (MR02–MR03)These control bits are used to select whether data is input with
external horizontal, vertical and blanking sync signals or if the data
is input with embedded EAV/SAV codes.
An Asynchronous timing mode is also available using TSYNC,
SYNC and DV as input control signals. These control signals
have to be programmed by the user.
Figure 17 shows an example of how to program the ADV7196A to
accept a different high definition standard but SMPTE293M,
SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
Input Standard (MR04)Select between 525p progressive scan input or 625p progressive
scan input.
Reserved (MR05)A “0” must be written to this bit.
DV Polarity (MR06)This control bit allows to select the polarity of the DV input
control signal to be either active high or active low. This is in
order to facilitate interfacing from I to P Converters which use
an active low blanking signal output.
Macrovision (MR07)To enable Macrovision this bit must be set to “1.”
Figure 16.Mode Register 0
Table II must be followed when programming the control sig-
nals in Async Timing Mode.
Table II.Truth TableFigure 17.Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility
Figure 18.DV Input Control Signal in Relation to Video Output Signal
ADV7196A
VBI Open (MR14)This bit enables or disables the facility of VBI data insertion during
the Vertical Blanking Interval.
For this purpose Lines 13 to 42 of each frame can be used for VBI
when SMPTE293M standard is used, or Lines 6 to 43 when
ITU-R.BT1358 standard is used.
Undershoot Limiter (MR15–MR16)This control limits the Y signal to a programmable level in the active
video region.
Available limit levels are –1.5 IRE, –6 IRE, –11 IRE.
Note that this facility is only available when Interpolation is enabled
(MR36 = “1”).
Sharpness Filter (MR17)This control bit enables or disables the Sharpness Filter mode. This
bit must be set to “1” for any values programmed into the Filter
Gain 1 Register to take effect. It must also be set to “1” when
Adaptive Filter mode is used.
Refer to Sharpness Filter control and Adaptive Filter control section.
Figure 19.Undershoot Limiter, Programmed to –6 IRE
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Figure 20 shows the various operations under the control of Mode
Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)When this bit is set to “0,” the pixel data input to the ADV7196A
is blanked such that a black screen is output from the DACs. When
this bit is set to “1,” pixel data is accepted at the input pins and
the ADV7196A outputs the standard set in “Output Standard
Selection” (MR01–00). This bit must be set to “1” to enable out-
put of the test pattern signals.
Input Format (MR11)It is possible to input data in 4:2:2 format or at 4:4:4 format at
27 MHz.
Test Pattern Enable (MR12)Enables or disables the internal test pattern generator.
Test Pattern Hatch/Frame (MR13)If this bit is set to “0,” a cross-hatch test pattern is output from the
ADV7196A (for example, in SMPTE293M 11 horizontal and 11
vertical white lines, four pixels wide are displayed against a black
background). The cross-hatch test pattern can be used to test
monitor convergence.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7196A.
The color of the lines or the frame/field is by default white but can
be programmed to be any color using the Color Y, Color Cr,
Color Cb registers.
Figure 20.Mode Register 1
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)Figure 22 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)This control bit delays the Y signal with respect to the falling edge
of the horizontal sync signal by up to four pixel clock cycles.
Figure 21 demonstrates this facility.
Color Delay (MR23–MR25)This control allows delay of the color signals with respect to the
falling edge of the horizontal sync signal by up to four pixel clock
cycles. Figure 21 demonstrates this facility.
CGMS Enable (MR26)When this bit is set to “1,” CGMS data is inserted on Line 41 in
525p mode. The CGMS conforms: to CGMS-A EIA-J CPR1204-1,
Transfer Method of Video ID information using vertical blanking
interval (525p System), March 1998 and IEC61880, 1998, video
systems (525/60)—video and accompanied data using the vertical
blanking interval—analogue interface.
The CGMS data bits are programmed into the CGMS Data
Registers 0–2. For more information refer to CGMS Data
Registers section.
CGMS CRC (MR27)This bit enables the automatic Cyclic Redundancy Check when
CGMS is enabled.
Figure 21.Y and Color Delay
Figure 22.Mode Register 2
ADV7196A
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)Figure 24 shows the various operations under the control of Mode
Register 4.
MR4 BIT DESCRIPTION
Timing Reset (MR40)Toggling MR40 from low to high and low again resets the inter-
nal horizontal and vertical timing counters.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)Figure 25 shows the various operations under the control of
Mode Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)This bit is reserved for the revision code.
RGB Mode (MR51)When RGB mode is enabled (MR51 = “1”) the ADV7196A accepts
unsigned binary RGB data at its input port. This control is also
available in Async Timing Mode.
Sync on PrPb (MR52)By default the color component output signals Pr, Pb do not
contain any horizontal sync pulses. They can be inserted when
MR52 = “1.” This facility is only available when Output Standard
Selection has been set to EIA-770.2 (MR01–00 = “00”) or Full
Input Range (MR01–00 = “10”).
This control is not available in RGB mode.
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)Figure 23 shows the various operations under the control of Mode
Register 3.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)When this bit is set to “1” the ADV7196A reverts to HDTV mode
(refer to HDTV mode section). When set to “0” the ADV7196A
is set up in Progressive Scan Mode (PS Mode).
Reserved (MR31–MR32)A “0” must be written to these bits.
DAC A Control (MR33)Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Interpolation (MR36)This bit enables the second stage interpolation filters. When this
bit is enabled (MR36 = “1”). data is send at 54 MHz to the DAC
output stage. After Reset it is recommended to toggle this bit.
Before toggling this bit 3Ehex must be written to address 09hex
to guarantee correct operations.
Reserved (MR37)A zero must be written to this bit.
Figure 23.Mode Register 3
Figure 24.Model Register 4
