ADV7177KSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACsGENERAL DESCRIPTIONProgrammable Luma Filters (Low-Pass/Notch/Extended)The ADV7177/ADV7178 is an int ..
ADV7177KSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACsspecifications T to T unless otherwise noted.)AA REF SET MIN MAX1Parameter Conditions Min Typ Max U ..
ADV7178KS ,Integrated Digital CCIR-601 to PAL/NTSC Video EncoderFEATURES Programmable Subcarrier Frequency and PhaseITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder ..
ADV7179BCP ,Chip Scale NTSC/PAL Video EncoderSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADV7179BCP-REEL ,Chip Scale PAL/NTSC Video Encoder with Advanced Power Managementapplications extended SSAF, CIF, and QCIF Mobile phones Programmable chroma filters (low-pass [0.6 ..
ADV7179BCPZ , Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
AM27C512-90PC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C64 , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120JC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-150DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
ADV7177KSZ
Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACs
REV.B
Integrated Digital CCIR-601
to PAL/NTSC Video Encoder
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 9-Bit Video DACs
Integral Nonlinearity <1 LSB at 9 Bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz Crystal/Clock Required (�2 Oversampling)
75 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV or RGB
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
Full Video Output Drive or Low Signal Drive Capability
34.7 mA Max into 37.5 � (Doubly Terminated 75R)
5 mA Min with External Buffers
Programmable Simultaneous Composite and S-VHS
(VHS) Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
OSD Support (AD7177 Only)
Programmable Multimode Master/Slave Operation
Macrovision AntiTaping Rev 7.01 (ADV7178 Only)1
Closed Captioning Support
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C®-Compatible)
Single Supply 5 V or 3 V Operation
Small 44-Lead PQFP Package
Synchronous 27 MHz/13.5 MHz Clock O/P
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable Systems (Set-Top Boxes/IRDs), Digital TVs,
CD Video/Karaoke, Video Games, PC Video/Multimedia
FUNCTIONAL BLOCK DIAGRAM*. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
NOTES
1This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is licensed for
noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available ITU-R and CCIR are
used interchangeably in this document (ITU-R has replaced CCIR recommendations).I2C is a registered trademark of Philips Corporation.
(continued on page 9)
GENERAL DESCRIPTIONThe ADV7177/ADV7178 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8- or 16-bit component
video data into a standard analog baseband television signal
ADV7177/ADV7178–SPECIFICATIONSSTATIC PERFORMANCE
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.All digital input pins except pins RESET, OSD0 and CLOCK.Excluding all digital input pins except pins RESET, OSD0 and CLOCK.Full drive into 75Ω load.Minimum drive current (used with buffered/scaled output load).Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 18.5 mA output per DAC) to drive all three DACs. Turning off individual
DACs reduces IDAC correspondingly.ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2 unless otherwise noted.)5 V SPECIFICATIONS
ADV7177/ADV7178
3.3 V SPECIFICATIONS(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2 unless otherwise noted.)NOTES
11The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12Temperature range TMIN to TMAX: 0°C to 70°C.
13Guaranteed by characterization.
14All digital input pins except pins RESET, OSD0 and CLOCK.
15Excluding all digital input pins except pins RESET, OSD0 and CLOCK.
16Full drive into 75Ω load.
17DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 150 Ω).
18Minimum drive current (used with buffered/scaled output load).
19Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.
10IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all three DACs. Turning off individual
DACs reduces IDAC correspondingly.
11ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
ADV7177/ADV7178–SPECIFICATIONS
5 V DYNAMIC SPECIFICATIONS
(VAA = 4.75 V–5.25 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2
unless otherwise noted.)FILTER CHARACTERISTICS
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 5.Guaranteed by characterization.
Specifications subject to change without notice.
ADV7177/ADV7178
3.3 V DYNAMIC SPECIFICATIONS
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2
unless otherwise noted.)FILTER CHARACTERISTICS
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.Temperature range TMIN to TMAX: 0°C to 70°C.These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 5.Guaranteed by characterization.
Specifications subject to change without notice.
ADV7177/ADV7178
5 V TIMING SPECIFICATIONS
(VAA = 4.75 V–5.25 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2 unless
otherwise noted.)RESET CONTROL
INTERNAL CLOCK CONTROL
OSD TIMING
NOTESThe max/min specifications are guaranteed over this range.Temperature range TMIN to TMAX: 0°C to 70°C.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCK
Specifications subject to change without notice.
ADV7177/ADV7178
3.3 V TIMING SPECIFICATIONS
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2 unless
otherwise noted.)NOTESThe max/min specifications are guaranteed over this range.Temperature range TMIN to TMAX: 0°C to 70°C.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCK
Specifications subject to change without notice.
ADV7177/ADV7178Figure 1.MPU Port Timing Diagram
Figure 2.Pixel and Control Data Timing Diagram
Figure 3.Internal Timing Diagram
Figure 4.OSD Timing Diagram
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . 260°C
Analog Outputs to GND2 . . . . . . . . . . . . GND – 0.5 V to VAA
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Analog output short circuit to any power supply or common can be of an
indefinite duration.
ORDERING GUIDE
PACKAGE THERMAL PERFORMANCEThe 44-lead PQFP package used for this device has a junction-
to-ambient thermal resistance (θJA) in still air on a four-layer
PCB of 53.2°C/W. The junction-to-case thermal resistance (θJC)
is 18.8°C/W.
Care must be taken when operating the part in certain condi-
tions to prevent overheating. Table I illustrates what conditions
are to be used when using the part.
Table I.Allowable Operating Conditions for ADV7177/
ADV7178 in 44-Lead PQFP PackageNOTESDAC ON, Double 75R refers to a condition where the DACs are terminated
into a double 75R load and low power mode is disabled.DAC ON, Low Power refers to a condition where the DACs are terminated in a
double 75R load and low power mode is enabled.DAC ON, Buffered refers to a condition where the DAC current is reduced to
5 mA and external buffers are used to drive the video loads.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7177/ADV7178 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
compatible with worldwide standards. The 4:2:2 YUV video data
is interpolated to two times the pixel rate. The color-difference
components (UV) are quadrature modulated using a subcarrier
frequency generated by an on-chip 32-bit digital synthesizer
(also running at two times the pixel rate). The two times pixel
rate sampling allows for better signal-to-noise ratio. A 32-bit
DDS with a 9-bit look-up table produces a superior subcarrier in
terms of both frequency and phase. In addition to the composite
output signal, there is the facility to output S-Video (Y/C) video,
YUV or RGB video.
Each analog output is capable of driving the full video-level
(34.7 mA) signal into an unbuffered, doubly terminated 75 Ω load.
With external buffering, the user has the additional option to scale
back the DAC output current to 5 mA min, thereby significantly
reducing the power dissipation of the device.
The ADV7177/ADV7178 also supports both PAL and NTSC
square pixel operation.
The output video frames are synchronized with the incoming data
timing reference codes. Optionally, the encoder accepts (and can
generate) HSYNC, VSYNC, and FIELD timing signals. These
timing signals can be adjusted to change pulsewidth and position
while the part is in the master mode. The encoder requires a
single two times pixel rate (27 MHz) clock for standard operation.
Alternatively, the encoder requires a 24.5454MHz clock for
NTSC or 29.5 MHz clock for PAL square pixel mode operation.
All internal timing is generated on-chip.
The ADV7177/ADV7178 modes are set up over a two-wire serial
bidirectional port (I2C-Compatible) with two slave addresses.
Functionally the ADV7178 and ADV7177 are the same with the
exception that the ADV7178 can output the Macrovision anticopy
algorithm, and OSD is only supported on the ADV7177.
The ADV7177/ADV7178 is packaged in a 44-lead thermally
enhanced PQFP package.
(continued from page 1)
ADV7177/ADV7178
PIN CONFIGURATION
RSET
VREF
DAC A
VAA
GND
VAA
DAC B
BLANK
P13
P14
P15
FIELD/
VSYNC
ALSB
VAA
CLOCK/2
P10
P11
P12
OSD_EN
DAC C
COMP
SDATA
SCLOCK
GND
GND
RESET
CLOCKCLOCKGNDP3P2P1OSD_2OSD_1OSD_0
HSYNC
PIN FUNCTION DESCRIPTIONS
TPC 1.NTSC Low-Pass Filter
TPC 2.NTSC Notch Filter
TPC 3.PAL Low-Pass Filter
TPC 4.PAL Notch Filter
TPC 5.NTSC/PAL Extended Mode Filter
TPC 6.NTSC UV Filter
ADV7177/ADV7178TPC 7.PAL UV Filter
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to from three
data paths. Y typically has a range of 16 to 235, Cr and Cb typi-
cally have a range of 128 ± 112; however, it is possible to input data
from 1 to 254 on both Y, Cb and Cr. The ADV7177/ADV7178
supports PAL (B, D, G, H, I, N, M) and NTSC (with and without
Pedestal) standards. The appropriate SYNC, BLANK and Burst
levels are added to the YCrCb data. Macrovision antitaping
(ADV7178 only), closed captioning, OSD (ADV7177 only),
and teletext levels are also added to Y, and the resultant data is
interpolated to a rate of 27 MHz. The interpolated data is filtered
and scaled by three digital FIR filters.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chrominance
signal. The luma (Y) signal can be delayed 1–3 luma cycles (each
cycle is 74 ns) with respect to the chroma signal. The luma and
chroma signals are then added together to make up the composite
video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively
analog YUV data can be generated instead of RGB.
The three 9-bit DACs can be used to output:RGB VideoYUV VideoOne Composite Video Signal + LUMA and CHROMA(S-Video).
Alternatively, each DAC can be individually powered off if
not required.
Video output levels are illustrated in Appendix 3.
INTERNAL FILTER RESPONSEThe Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low-pass responses, PAL/
NTSC subcarrier notch responses and a PAL/NTSC extended
response. The U and V filters have a 1.0/1.3 MHz low-pass
response for NTSC/PAL. These filter characteristics are illus-
trated in the Typical Performance Characteristics (TPCs 1 to 7).
COLOR BAR GENERATIONThe ADV7177/ADV7178 can be configured to generate 100/7.5/
75/7.5 color bars for NTSC or 100/0/75/0 for PAL color bars. These
are enabled by setting MR17 of Mode Register 1 to Logic“1.”
Square Pixel ModeThe ADV7177/ADV7178 can be used to operate in square pixel
mode. For NTSC operation an input clock of 24.5454 MHz is
required. Alternatively an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
Color Signal ControlThe color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
Burst Signal ControlThe burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC Pedestal ControlThe pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
Figure 5.Luminance Internal Filter Specifications
Figure 6.Chrominance Internal Filter Specifications
PIXEL TIMING DESCRIPTIONThe ADV7177/ADV7178 can operate in either 8-bit or 16-bit
YCrCb Mode.
8-Bit YCrCb ModeThis default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb ModeThis mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
OSDThe ADV7177 supports OSD. There are twelve 8-bit OSD regis-
ters, loaded with data from the four most significant bits of Y, Cb,
Cr input pixel data bytes. A choice of eight colors can, therefore,
be selected via the OSD_0, OSD_1, OSD_2 pins, each color
being a combination of 12 bits of Y, Cb, Cr pixel data. The
display is under control of the OSD_EN pin. The OSD window
can be an entire screen or just one pixel, its size may change by
using the OSD_EN signal to control the width on a line-by-line
basis. Figure 4 illustrates OSD timing on the ADV7177.
VIDEO TIMING DESCRIPTIONThe ADV7177/ADV7178 is intended to interface to off-the-shelf
MPEG1 and MPEG2 decoders. Consequently, the ADV7177/
ADV7178 accepts 4:2:2 YCrCb pixel data via a CCIR-656 pixel
port, and has several video timing modes of operation that allow it
to be configured as either system master video timing generator
or a slave to the system video timing generator. The ADV7177/
ADV7178 generates all of the required horizontal and vertical
timing periods and levels for the analog video outputs.
The ADV7177/ADV7178 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
In addition, the ADV7177/ADV7178 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
The ADV7177/ADV7178 has four distinct master and four
distinct slave timing configurations. Timing Control is established
with the bidirectional SYNC, BLANK, and FIELD/VSYNC
pins. Timing Mode Register 1 can also be used to vary the timing
pulsewidths and where they occur in relation to each other.
Vertical Blanking Data InsertionIt is possible to allow encoding of incoming YCbCr data on those
lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see TPCs). This mode of operation is called “Partial Blank-
ing” and is selected by setting MR31 to 1. It allows the insertion of
any VBI data (Opened VBI) into the encoded output waveform.
This data is present in digitized incoming YCbCr data stream
(e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI
may be blanked (no VBI data inserted) on these lines by setting
MR31 to 0.
ADV7177/ADV7178Figure 7.Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656):Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7177/ADV7178 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. Mode 0 is illustrated in Figure 7. The HSYNC, FIELD/VSYNC and BLANK (if not
used) pins should be tied high during this mode.
Mode 0 (CCIR-656):Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7177/ADV7178 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) time
codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 8 (NTSC) and Figure 9 (PAL). The H, V and F transitions relative
to the video waveform are illustrated in Figure 10.
Figure 9.Timing Mode 0 (PAL Master Mode)
Figure 10.Timing Mode 0 Data Transitions (Master Mode)
ADV7177/ADV7178
Mode 1:Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7177/ADV7178 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled,
the ADV7177/ADV7178 automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 11 (NTSC) and Figure 12 (PAL).
Figure 11.Timing Mode 1 (NTSC)
Mode 1:Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 11 (NTSC) and Figure 12 (PAL). Figure 13 illustrates the HSYNC,
BLANK and FIELD for an odd or even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2Y
HSYNC
BLANKFigure 13.Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2:Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7177/ADV7178 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all nor-
mally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL).
Figure 14.Timing Mode 2 (NTSC)
ADV7177/ADV7178Figure 15.Timing Mode 2 (PAL)
Mode 2:Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7177/ADV7178 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). Figure 16 illustrates the HSYNC,
BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 17 illustrates the HSYNC, BLANK and
VSYNC for an odd-to-even field transition relative to the pixel data.
Figure 16.Timing Mode 2 Even-to-Odd Field Transition Master/Slave
Figure 17.Timing Mode 2 Odd-to-Even Field Transition Master/Slave
Mode 3:Master/Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7177/ADV7178 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 18 (NTSC) and Figure 19 (PAL).
Figure 18.Timing Mode 3 (NTSC)
ADV7177/ADV7178Figure 19.Timing Mode 3 (PAL)
POWER-ON RESETAfter power-up, it is necessary to execute a reset operation. A reset
occurs on the falling edge of a high-to-low transition on the RESET
pin. This initializes the pixel port so that the pixel inputs, P7–P0
are selected. After reset, the ADV7177/ADV7178 is automatically
set up to operate in NTSC mode. Subcarrier frequency code
21F07C16HEX is loaded into the subcarrier frequency registers.
All other registers, with the exception of Mode Register 0, are
set to 00H. All bits in Mode Register 0 are set to Logic Level
“0” except Bit MR02. Bit MR02 of Mode Register 0 is set to
Logic Level “1.” This enables the 7.5 IRE pedestal.
MPU PORT DESCRIPTIONThe ADV7178 and ADV7177 support a two-wire serial (I2C-
Compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus. Each
slave device is recognized by a unique address. The ADV7178
and ADV7177 each have four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 20 and Figure 21. The LSB
sets either a read or write operation. Logic Level “1” corresponds to
a read operation, while Logic Level “0” corresponds to a write
operation. A1 is set by setting the ALSB pin of the ADV7177/
ADV7178 to Logic Level “0” or Logic Level “1.”
Figure 20.ADV7177 Slave Address
Figure 21.ADV7178 Slave Address
