ADV7160KS220 ,96-Bit, 220 MHz True-Color Video RAM-DACspecifications T to T unless otherwise noted.)L MIN MAXParameter Min Typ Max Units Test Conditions ..
ADV7162KS140 ,96-Bit, 220 MHz True-Color Video RAM-DACGENERAL DESCRIPTION8-Bit (Pseudo)The ADV7160/ADV7162® is a 96-bit pixel port Video RAM-Pixel Data S ..
ADV7170KS ,Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power ManagementSPECIFICATIONSAA REF SET MIN MAX1Parameter Conditions Min Typ Max Units3STATIC PERFORMANCEResolutio ..
ADV7170KSU ,Digital PAL/NTSC Video Encoder with 10-Bit SAFF™ and Advanced Power Management & Macrovision 7.01Specifications subject to change without notice.–2– REV. AADV7170/ADV71711 2 (V = 3.0 V – 3.6 V , V ..
ADV7170KSU-REEL ,Digital PAL/NTSC Video Encoder with 10-Bit SAFF™ and Advanced Power Management & Macrovision 7.01Digital PAL/NTSC Video Encoder with 10-Bit™aSSAF and Advanced Power Management1ADV7170/ADV7171
ADV7170KSUZ ,Digital PAL/NTSC Video Encoder with 10-Bit SAFF™ and Advanced Power Management & Macrovision 7.01SPECIFICATIONSAA REF SET MIN MAX1Parameter Conditions Min Typ Max Unit3STATIC PERFORMANCEResolution ..
AM27C512-150DE , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150DIB , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150PC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
ADV7160KS220-ADV7162KS140
96-Bit, 220 MHz True-Color Video RAM-DAC
REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
96-Bit, 220 MHz
True-Color Video RAM-DAC© Analog Devices, Inc., 1995
MODES OF OPERATION
1600×1200×
30/24-Bit Resolution @ 85 Hz Screen Refresh
1600×1200×
16/15-Bit Resolution @ 85 Hz Screen Refresh
1600×1200×
8-Bit Resolution @ 85 Hz Screen Refresh
APPLICATIONS
Windows Accelerators
High Resolution, True Color Graphics
Professional Color Prepress Imaging
Digital TV (HDTV, Digital Video)
SPEED GRADES
@ 220 MHz
@ 170 MHz
@ 140 MHz
GENERAL DESCRIPTIONThe ADV7160/ADV7162® is a 96-bit pixel port Video RAM-
DAC with color enhanced triple 10-bit DACs. The device also
includes a PLL and 64 × 64 hardware cursor. The ADV7160/
ADV7162 is specifically designed for use in the graphics sub-
system of high performance, color graphics workstations and
windows accelerators.
(Continued on page 15)
FEATURES
96-Bit Pixel Port for 1600 × 1280 × 24 Screen Resolution
220 MHz, 24-Bit (30-Bit Gamma Corrected) True-Color
Triple 10-Bit “Gamma Correcting” D/A Converters
2% (max) DAC to DAC Color Matching
Triple 256 × 10 (256 x 30) Color Palette RAM
On-Board User Definable Cursor (64 × 64 × 2)
Three Color Overlay
Cursor Palette RAM
Fully Programmable On-Board PLL
RS-343A/RS-170 Compatible RGB Analog Outputs
Tri-Level SYNC Functionality
TTL Compatible Digital Inputs
Standard MPU I/O Interface
Programmable Pixel Port: 24-Bit, 16-Bit, 15-Bit &
8-Bit (Pseudo)
Pixel Data Serializer:
Multiplexed Pixel Input Ports; 2:1, 4:1, 8:1
+5 V CMOS Monolithic Construction
160-Lead Plastic Quad Flatpack (QFP): ADV7162
160-Lead “Thermally Enhanced” QFP (PQUAD): ADV7160
FUNCTIONAL BLOCK DIAGRAMADV is a registered trademark of Analog Devices, Inc.
TDO
GNDTDITCKTMSC1D9–D0C0
PIXEL
DATA
(P7-P0)
ODD/EVEN
LOADIN
SCKIN
LOADOUT
COMP
IOG
IOB
PLLREF
CLOCK
PALETTE
SELECTS
(PS0, PS1)
SYNCOUT
IOR
CLOCK
PRGCKOUT
SCKOUT
TRISYNC
SYNC
BLANKR/W
VREF
RSET
VAA
ADV7160/ADV7162–SPECIFICATIONSNOTES±5% for all versions.Temperature range (TMIN to TMAX): 0°C to +70°C.Pixel Port is continuously clocked with data corresponding to a linear ramp. TJ = 100oC.Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
(VAA1 = +5 V; VREF = +1.235 V; RSET = 280 Ω. IOR, IOG, IOB (RL = 37.5 Ω,
CL = 10 pF). All specifications TMIN to TMAX2 unless otherwise noted.)
CLOCK CONTROL AND PIXEL PORT4
ANALOG OUTPUTS7
TIMING CHARACTERISTICS1 (VAA2= +5 V; VREF = +1.235 V; RSET = 280 Ω. IOR, IOG, IOB (RL = 37.5 Ω, CL = 10 pF). All
specifications TMIN to TMAX3 unless otherwise noted.)
ADV7160/ADV7162
MPU PORT 8,9NOTES
General NotesTTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points.
ECL inputs (CLOCK, CLOCK) are VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points.
Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
Data-Bus (D0–D9) loaded as shown in Figure 1.
Digital output load for LOADOUT, PRGCKOUT & SCKOUT ≤ 30 pF.±5% for all versionsTemperature range (TMIN to TMAX); 0°C to +70°C.
Notes on PIXEL PORTPixel Port consists of the following inputs:
Pixel Inputs:RED [A, B, C, D]GREEN [A, B, C, D] BLUE [A, B, C, D]
Palette Selects:PS0 [A, B, C, D];PS1[A, B, C, D]
Pixel Controls:SYNC, BLANK, TRISYNC, ODD/EVEN
Clock Inputs:CLOCK, CLOCK, LOADIN, SCKIN
Clock Outputs:LOADOUT, PRGCKOUT, SCKOUTτ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode:
2:1 multiplexing;τ = CLOCK × 2= 2 × t1ns
4:1 multiplexing;τ = CLOCK × 4= 4 × t1ns
8:1 multiplexing;τ = CLOCK × 8= 8 × t1nsThese fixed values for Pipeline Delay are valid under conditions where t10 and τ-t11 are met. If either t10 or τ-t11 are not met, the part will operate but the Pipeline
Delay is increased.
Notes on ANALOG OUTPUTSOutput delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Output rise/fall time measured between the 10% and 90% points of full-scale transition.
Transition time measured from the 50% point of full scale transition to the output remaining within 2% of the final output value. (Transition time does not include
clock and data feedthrough).
Notes on MPU PORTt23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.t25 and t26 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured numbers are
then extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the times t25 and t26, quoted in the Timing Characteristics are the
true values for the device and as such are independent of external loading capacitances.
Specifications subject to change without notice.
100pF
TO OUTPUT
PIN
ISINK
+2.1VFigure 1.Load Circuit for Databus Access and Relinquish Times
JTAG PORTNOTESTTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.±5% for all versions.Temperature range (TMIN to TMAX); 0°C to +70°C.Jitter is measured by triggering on the output clock, delayed by 15 μs and then measuring the time period from the trigger edge to the next edge of the output clock
after the delay. This measurement is repeated multiple times and the RMS value is determined.
Specifications subject to change without notice.
TCK
TMS, TDI
DIGITAL
INPUT
TDO
TDOFigure 2.JTAG Timing
TIMING CHARACTERISTICS (Cont.)1(VAA2= +5 V; VREF = +1.235 V; RSET = 280 Ω. IOR, IOG, IOB (RL = 37.5 Ω, CL =10 pF).
All specifications TMIN to TMAX3 unless otherwise noted.)
ADV7160/ADV7162
Timing Waveforms
CLOCK
CLOCK
LOADOUT
(2:1 MULTIPLEXING)
LOADOUT
(4:1 MULTIPLEXING)
LOADOUT
(8:1 MULTIPLEXING)Figure 3.LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
t9
LOADIN
PIXEL INPUT
DATAFigure 4.LOADIN vs. Pixel Input Data
AN+2 ... HN+2
CLOCK
LOADOUT
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)Figure 5.Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (8:1 Multiplex Mode)
AN+2 ... HN+2AN+1 ... HN+1AN–1 ... HN–1
CLOCK
LOADOUT
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)Figure 6.Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (8:1 Multiplex Mode)
ADV7160/ADV7162
CLOCK
LOADOUT
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)Figure 7.Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)
OUTPUT PIPELINE
AN+2 ... DN+2
CLOCK
LOADOUT
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)Figure 8.Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)
CLOCK
LOADOUT
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)Figure 9. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
CLOCK
LOADOUT
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)Figure 10. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
ADV7160/ADV7162
CLOCK
t12
PRGCKOUT
(CLOCK/4)
PRGCKOUT
(CLOCK/8)
PRGCKOUT
(CLOCK/16)
PRGCKOUT
(CLOCK/32)Figure 11.Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT)
t13
t15
t14
SCKIN
BLANK
SCKOUT
BLANKING PERIOD
END OF SCAN LINE (N)START OF SCAN LINE (N+1)Figure 12.Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)
IOR
IOG
IOB
SYNCOUT
ANALOG
OUTPUTS
CLOCK
NOTE:
THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY, THE
ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLLITUDE
W.R.T THE CLOCK WAVEFORM.
SYNCOUT IS A DIGITAL VIDEO OUTPUT SIGNAL.
t16 IS THE ONLY RELEVANT TIMING SPECIFICATION FOR SYNCOUT.Figure 13.Analog Output Response vs. CLOCK
R/W, C0, C1
D0–D9
(READ MODE)
D0–D9
(WRITE MODE)Figure 14.Microprocessor Port (MPU) Interface Timing
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Voltage on Any Digital Pin . . . . .GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . . . .0°C to +70°C
Storage Temperature (TS) . . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . .+150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+260°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . .+220°C
Analog Outputs to GND2 . . . . . . . . . . . .GND – 0.5 V to VAA
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
160-Lead QFP Configuration
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7160/ADV7162 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING INFORMATION1, 2, 3
Dot Clock SpeedNOTESAll devices are specified for 0°C to +70°C operation.Contact Sales Office for latest information on package design.ADV7160 is packaged in a 160-pin plastic power quad flatpack, QFP with
heatsink embedded.ADV7162 is packaged in a standard 160-pin plastic quad flatpack, QFP.
ADV7160/ADV7162
ADV7160/ADV7162 PIN ASSIGNMENTS
PIN FUNCTION DESCRIPTION
MnemonicFunctionRED (R0A...R0B – R7A...R7D), GREEN (G0A...G0D – G7A...G7D), BLUE (B0A...B0D – B7A...B7D):
Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, Green and Blue.
Each bit is multiplexed [A-D] 4:1 or 2:1. It can be configured for 24-Bit True-Color Data, 8-Bit
Pseudo-Color Data, 16-Bit True-Color and 15-Bit True-Color Data formats. In 8-Bit Pseudo-Color
Mode, there is a special case whereby 8:1 multiplexing is also available. It will be explained in more
detail later. Pixel Data is latched into the device on the rising edge of LOADIN.
PS0A ...PS0D, PS1A ...PS1D
Palette Priority Selects (TTL Compatible Inputs): The eight PS inputs provide two Bits after input
multiplexing. These pixel port select inputs can be configured for three separate functions. In Overlay
Mode, these inputs provide a three color overlay function. With any value other than “00” on the
overlay inputs, the color displayed comes from the overlay palette instead of the main pixel inputs.
For the ADV7160, in Bypass Mode, PS1 specifies for each pixel whether it should pass through the
Color Matrix and Color Palette or bypass the Matrix and Palette. PS0 acts as an overlay input. (This
mode is not available for the ADV7162.) Palette Select Mode is used to multiplex the RGB outputs of
a number of devices. When the palette mode inputs match the PS bits in the mode register, the part
operates as normal. When there is a mismatch, the RGB outputs are switched to zero, allowing the
RGB outputs of another device to drive the monitor.
LOADINPixel Data Load Input (TTL Compatible Input): This input latches the multiplexed pixel data, in-
cluding PS0-PS1, BLANK, TRISYNC, SYNC and ODD/EVEN into the device.
LOADOUTPixel Data Load Output (TTL Compatible Output): This output control signal runs at a divided
down frequency of the pixel clock. Its frequency is a function of the multiplex rate. It can be used to
directly or indirectly drive LOADIN.
fLOADOUT = fCLOCK/M
where
(M = 2 for 2:1 Multiplex Mode)
(M = 4 for 4:1 Multiplex Mode)
(M = 8 for 8:1 Multiplex Mode)
PRGCKOUTProgrammable Clock Output (TTL Compatible Output):This output control signal runs at a divided
down frequency of the pixel Clock. Its frequency is user programmable and is determined by bits
CR30 and CR31 of Command Register 3.
fPRGCKOUT = fCLOCK/N
where N = 4, 8, 16 & 32
SCKINVideo Shift Clock Input (TTL Compatible Input): The signal on this input is internally gated syn-
chronously with the BLANK signal. The resultant output, SCKOUT, is a video clocking signal that
is stopped during video blanking periods. It is normally driven by a divided down version of the
CLOCK frequency.
SCKOUTVideo Shift Clock Output (TTL Compatible Output): This output is a synchronously gated version of
SCKIN and BLANK. SCKOUT is a video clocking signal that is stopped during video blanking
periods.
CLOCK, CLOCKClock Inputs (ECL Compatible Inputs): These differential clock inputs are designed to be driven by
ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel
clock rate of the system.
PLLREFPLL Clock Input (TTL Compatible Input): This clock input is designed to be driven by TTL logic
levels. The PLL is then configured to output a specific frequency depending on the PLL Registers.
See PLL section for more detail.
BLANKComposite Blank (TTL Compatible Input): This video control signal drives the analog outputs to the
blanking level.
SYNCComposite-Sync Input (TTL Compatible Input): This video control signal drives any of the analog
outputs to the SYNC level. It is only asserted during the blanking period. CR22 in Command
Register 2 must be set if SYNC is to be decoded onto the IOG analog output, CR41 in Command
Register 4 must be set if SYNC is to be decoded onto the IOR analog output, CR42 in Command
Register 4 must be set if SYNC is to be decoded onto the IOB analog output, otherwise the SYNC
input is ignored.
ADV7160/ADV7162
MnemonicFunctionSYNCOUTComposite-Sync Output (TTL Compatible Output). This video output is a delayed version of
SYNC. The delay corresponds to the number of pipeline stages of the device.
TRISYNCComposite-Sync HDTV Control (TTL Compatible Output). This video input is enabled using Bit
CR17 in Command Register 1. When TRISYNC is low, any DAC output which has Sync enabled,
goes to the tri-sync level. As with the SYNC input, it should only be activated while BLANK is low.
D9–D0Data Bus (TTL Compatible Input/Output Bus). Data, including color palette values and device con-
trol information is written to and read from the device over this 10-bit, bidirectional databus. 10-bit
data or 8-bit data can be used. The databus can be configured for either 10-bit parallel data or byte
data (8+2) as well as standard 8-bit data. Any unused bits of the data bus should be terminated
through a resistor to either the digital power plane (VCC) or GND.
ODD/EVENOdd/Even Control (TTL Compatible Input). This input indicates which field of the frame is being
displayed. It is required to ensure proper operation of the ADV7160/ADV7162 cursor when inter-
laced display mode is selected. It is ignored when noninterlaced display mode is selected. This input
should change only during the vertical blank period. It is assumed that an odd field will always follow
an even field and vice versa.Chip Enable (TTL Compatible Input). This input must be at Logic “0” when writing to or reading
from the device over the data bus (D0–D9). Internally, data is latched on the rising edge of CE.
R/WRead/Write Control (TTL Compatible Input). This input determines whether data is written to or
read from the device’s registers and color palette RAM. R/W and CE must be at Logic “0” to write
data to the part. R/W must be at Logic “1” and CE at Logic “0” to read from the device.
C0, C1Command Controls (TTL Compatible Inputs). These inputs determine the type of read or write op-
eration being performed on the device over the data bus, (see Interface Truth Table). Data on these
inputs is latched on the falling edge of CE.
IOR, IOG, IOBRed, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs
are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 75 Ω loads.
VREFVoltage Reference Input (Analog Input): An external 1.235 V voltage reference is required to drive
this input. An AD589 (2-terminal voltage reference) or equivalent is recommended. (Note: It is not
recommended to use a resistor network to generate the voltage reference.)
RSETOutput Full Scale Adjust Control (Analog Input). A resistor connected between this pin and analog
ground controls the absolute amplitude of the output video signal. For a value of RSET of nominally
280 Ω, with 37.5 Ω termination and using CR43 and CR44 of Command Register 4 to set the DAC
Gain as shown, the required Video Standard can be achieved.
CR44CR43Video StandardDAC GainBlack to White0RS343A, Sync & Pedestal3996660 mV 17.62 mA1RS343A, Sync & No Pedestal4224699 mV 18.63 mA0RS343A, No Sync & No Pedestal4311714 mV 19.05 mA1RS170, Sync & Pedestal5592925 mV 24.67 mA
Alternatively, RSET can be calculated by the following equation:SET
DACGain×VREF
BlacktoWhiteCurrent
COMPCompensation Pin. A 0.1 μF capacitor should be connected between this pin and VAA.
VAAPower Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be connected
together to one common +5 V filtered analog power supply.
GND:Analog Ground. The part contains multiple ground pins, all should be connected together to the
system’s ground plane.
TMS, TCK,These four pins control the JTAG test access port.
TDI, TDOSee Appendix 6 for more detail
(Continued from page 1)
The ADV7160/ADV7162 integrates a number of graphic func-
tions onto one device allowing 24-bit direct True-Color (30-bit
Corrected-Color) operation at the maximum screen resolution
of 1600 × 1280 at a refresh rate of 85 Hz. The ADV7160/
ADV7162 integrates a 256 × 30 Color Palette RAM with three
high speed, 10-bit, digital-to analog converters (RGB DACs).
It also contains a user-definable, X-Windows compatible, 64 ×
64 × 2 cursor generator and associated RAM. An on-board
Overlay Palette RAM is also included. The device’s 96-bit Pro-
grammable Pixel Port enables various data formats to be input
to the part. An on-board clock and synchronization circuit
controls all clocking functions for both the part and graphics
subsystem.
There are two video data paths through the ADV7160/ADV7162.
One routes the data from the pixel port through the RAM to the
DACs, the other bypasses the RAM and routes data direct from
the pixel port to the DACs. Either path can be selected on a
pixel by pixel basis. This allows for the overlay of an active
video window on a graphics background.
The on-board palette priority select inputs enable multiple pal-
ette devices to be connected together for use in multipalette and
window applications. The part is controlled and programmed
through the microprocessor (MPU) port.
one TTL input signal PLLREF are required to get the part
operational. No additional signals or external glue logic are re-
quired to get the Pixel Port and Clock Control Circuit of the
part operational.
Figure 15.Multiplexed Color Inputs for the
ADV7160/ADV7162
Pixel Port (Color Data)The ADV7160/ADV7162 has 96 color data inputs. The part
has four (for 4:1 multiplexing) 24-bit wide direct color data in-
puts. These are user programmed to support a number of color
data formats including 24-bit True-Color, 16-bit True-Color,
15-bit True-Color in 4:1 and 2:1 multiplex modes, and 8-bit
Pseudo-Color (see “Multiplexing” section) in 8:1, 4:1 and 2:1
multiplex modes.
Color data is latched into the parts pixel port on every rising
edge of LOADIN (see Timing Waveform, Figure 4). The
required frequency of LOADIN is determined by the multiplex
rate, where
fLOADIN = fCLOCK/88:1 multiplex mode
fLOADIN = fCLOCK/44:1 multiplex mode
fLOADIN = fCLOCK/22:1 multiplex mode
CIRCUIT DETAILS AND
OPERATION
OVERVIEWDigital video or pixel data is latched into the ADV7160/ADV7162
over the devices Pixel Port. This data acts as a pointer to on-
board Color Palette RAM. The data at the RAM address pointed
to is latched to the digital-to-analog converters (DACs) and out-
put as an RGB analog video signal.
For the purposes of clarity of description, the ADV7160/ADV7162
is broken down into three separate functional blocks. These are:Pixel Port and Clock Control CircuitMPU Port, Registers and Color PaletteDigital-to-Analog Converters and Video Outputs
Pixel Port & Clock Control CircuitThe Pixel Port of the ADV7160/ADV7162 is directly interfaced
to the video/graphics pipeline of a computer graphics subsystem.
It is connected directly or through a gate array to the video
RAM of the systems Frame-Buffer (video memory). The pixel
port on the device consists of:
Color DataRED, GREEN, BLUE
Pixel ControlsSYNC, BLANK, TRISYNC
Palette SelectsPS0A-D, PS1A-D
The associated clocking signals for the pixel port include:
Clock InputsCLOCK, CLOCK, PLLREF,
LOADIN, SCKIN
Clock OutputsLOADOUT, PRGCKOUT,
SCKOUT
These on-board clock control signals are included to simplify in-
terfacing between the part and the frame buffer. Either two
The 30 bits of resolution, associated with the color look-up table
and triple 10-bit DAC, realizes 24-bit True-Color resolution,
while also allowing for the on-board implementation of linear-
ization algorithms, such as Gamma-Correction and Monitor
Callibration. This allows effective 30-bit True-Color operation.
The on-chip video clock controller circuit generates all the inter-
nal clocking and some additional external clocking signals. The
high accuracy, low jitter on board PLL eliminates the need for
an external high speed clock generator. The PLL can be pro-
grammed to produce a pixel clock that is a multiple of the PLL
reference clock.
The ADV7162 is packaged in a standard plastic 160-pin quad
flatpack (QFP).
The ADV7160 is packaged in a plastic 160-pin power quad
flatpack (PQUAD). Superior thermal distribution is achieved by
the inclusion of a copper heatslug, within the standard package
outline, to which the die is attached. This part is ideally suited
for high performance applications where external environmental
conditions are unpredictable and uncontrollable.
ADV7160/ADV7162Other pixel data signals latched into the device by LOADIN
include SYNC, BLANK, TRISYNC and PS0A-D – PS1A-D.
Internally, data is pipelined through the part by the differential
pixel clock inputs, CLOCK and CLOCK or by the internal
pixel clock generated by the PLL on-board. The LOADIN
control signal need only have a frequency synchronous relation-
ship to the pixel CLOCK (see “Pipeline Delay & On-Board
Calibration” section). A completely phase independent
LOADIN signal can be used with the ADV7160/ADV7162,
allowing the CLOCK to occur anywhere during the LOADIN
cycle.
Alternatively, the LOADOUT signal of the ADV7160/ADV7162
can be used. LOADOUT can be connected either directly or
indirectly to LOADIN. Its frequency is automatically set to the
correct LOADIN requirement.
SYNC, BLANKThe BLANK and SYNC video control signals drive the analog
outputs to the Blank and Sync levels respectively. These signals
are latched into the part on the rising edge of LOADIN. The
SYNC information is encoded onto the IOG analog signal
when Bit CR22 of Command Register 2 is set to “1,” the IOR
analog signal when Bit CR41 of Command Register 4 is set to
“1” and the IOB analog signal when Bit CR42 of Command
Register 4 is set to “1.” The SYNC input is ignored if CR22,
CR41 and CR42 are set to logic “0.”
SYNCOUTIn some applications where it is not permissible to encode
SYNC on green (IOG), blue (IOB), or red (IOR), SYNCOUT
can be used as a separate TTL digital SYNC output. This has
the advantage over an independent (of the ADV7160/ADV7162)
SYNC in that it does not necessitate knowing the absolute pipe-
line delay of the part. This allows complete independence
between LOADIN/Pixel Data and CLOCK. The SYNC input
is connected to the device as normal with Bit CR22 of Com-
mand Register 2, Bit CR41 of Command Register 4 and Bit
CR42 of Command Register 4 are set to “0” thereby preventing
SYNC from being encoded onto IOG, IOR and IOB. The out-
put signal generates a TTL SYNCOUT with correct pipeline
delay which is capable of directly driving the composite SYNC
signal of a computer monitor.
TRISYNCThis input is used to generate a HDTV Sync on any of the DAC
outputs. Bit CR17 of Command Register 1 is set to “1”, en-
abling TRISYNC. When TRISYNC is low, the analog output
which has Sync enabled goes to the tri-sync level.
PS0A-D–PS1A-D (Palette Priority Select Inputs)These multifunctional TTL compatible inputs can be config-
ured for three separate functions. The eight PS inputs are mul-
tiplexed to provide two bits which are used to provide one of
three different functions. The function is selected by Bit CR14
and Bit CR15 of Command Register 1.
CR15CR14Color Mode0Palette Select Mode1Bypass Mode Control (ADV7160 Only)0Overlay Color Mode1Ignore PS Inputs
However, in 8:1 Mode, for 8-Bit Pseudo Color, the unused Blue
Pixel Inputs are used to provide 8 extra PS inputs. The bypass
mode is unavailable in this case.
Palette Select ModeThese pixel port select inputs effectively determine whether the
devices RGB analog outputs are turned-on or shut down. When
the analog outputs are shut down, IOR, IOG and IOB are
forced to 0 mA regardless of the state of the pixel and control
data inputs. This state is determined on a pixel by pixel basis as
the PS0–PS1 inputs are multiplexed in exactly the same format
as the pixel port color data. These controls allow for switching
between multiple palette devices. If the values of PS0 and PS1
match the values programmed into bits MR16 and MR17 of the
Mode Register, then the device is selected, if there is no match
the device is effectively shut down.
Bypass Mode Control (ADV7160 Only)In this mode PS1 is used to switch between one of the color
modes through the Color Palette and one of the Palette Bypass
modes on a pixel by pixel basis. The color mode through the
palette is selected using Bits CR27–CR24 of Command Regis-
ter 2. The Bypass Color Mode is selected using Bits CR17 and
CR16 of Command Register 1. PS1 then switches between the
Palette Color Mode, and the Bypass Color Mode. The PS0 in-
put continues to act as an overlay input, allowing Overlay Color
1 to be displayed.
PS0PS1Color Mode0Palette Color Mode (CR27–CR24)1Bypass Color Mode (CR17–CR16)xOverlay Color 1
This mode is not available if using the ADV7162.
Overlay Color ModeIn this mode, the PS inputs provide control for a three color
overlay. Whenever the value other than “00” is placed on the
overlay inputs, the corresponding overlay color is displayed.
When the overlay inputs contain “00” the color is specified by
the main pixel inputs.
CLOCK CONTROL CIRCUITThe ADV7160/ADV7162 has an integrated Clock Control Cir-
cuit (Figure 16). This circuit is capable of both generating the
ADV7160/ADV7162’s internal clocking signals as well as exter-
nal graphics subsystem clocking signals. Total system synchro-
nization can be attained by using the parts output clocking
signals to drive the controlling graphics processor’s master clock
as well as the video frame buffers shift clock signals.
CLOCK, CLOCK InputsThe Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and CLOCK. These inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
LOADOUT
LOADIN
BLANK
SCKOUT
SCKIN
CLOCK
CLOCKPRGCKOUT
PLLREF
TRISYNC
SYNC
M IS A FUNCTION OF MULTIPLEX RATE
M = 8 IN 8:1 MULTIPLEX MODE
M = 4 IN 4:1 MULTIPLEX MODE
M = 2 IN 2:1 MULTIPLEX MODE
N IS INDEPENDENTLY PROGRAMMABLE
N = (4, 8, 16, 32)Figure 16.Clock Control Circuit of the ADV7160/ADV7162
CLOCK CONTROL SIGNALS
LOADOUTThe ADV7160/ADV7162 generates a LOADOUT control sig-
nal which runs at a divided down frequency of the pixel
CLOCK. The frequency is automatically set to the pro-
grammed multiplex rate, controlled by CR37 and CR36 of
Command Register 3.
fLOADOUT = fCLOCK/88:1 multiplex mode
fLOADOUT = fCLOCK/44:1 multiplex mode
fLOADOUT = fCLOCK/22:1 multiplex mode
The LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7160/ADV7162. This is most sim-
ply achieved by tying the LOADOUT and LOADIN pins to-
gether. Alternatively, the LOADOUT signal can be used to
drive the frame buffer’s shift clock signals, returning to the
LOADIN input delayed with respect to LOADOUT.
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between
LOADOUT and LOADIN (LOADOUT(1) and
LOADOUT(2)). LOADIN and Pixel Data must conform to
the setup and hold times (t8 and t9).
If however, it is required that the ADV7160/ADV7162 has
a fixed number of pipeline delays (tPD) LOADOUT and
LOADIN must conform to timing specifications t10 and τ–t11 as
illustrated in Figures 5 to 10.
Figure 17. LOADOOUT vs Pixel Clock
Pipeline Delay and Onboard CalibrationThe ADV7160/ADV7162 has a fixed number of pipeline delays
(tPD), so long as timings t10 and τ–t11 are met. However, if a
fixed number of pipeline delays is not a requirement, timings t10
and τ–t11 can be ignored, a calibration cycle must be run and
there is no restriction on LOADIN to LOADOUT timing. If
timings t10 and τ–t11 are not met, the part will function correctly
though with an increased number of pipeline delays. The
ADV7160/ADV7162 has on-board calibration circuitry which
synchronizes pixel data and LOADIN with the internal
ADV7160/ADV7162 clocking signals. Calibration can be per-
formed in two ways. During the device’s initialization sequence
by toggling two bits of the Mode Register, MR10 followed by
MR15 or by writing a “1” to Bit CR10 of Command Register 1
and a “0” to MR15 which executes a calibration on every
Vertical Sync.
PRGCKOUTThe PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 11). The rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT.
fPRGCKOUT = fCLOCK/N
where N = 4, 8, 16 or 32.
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCKIN, SCKOUTThese video memory signals are used to minimize external sup-
port chips. Figure 18 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). The resulting signal
is output on SCKOUT. Figure 12 of the Timing Waveform
section shows the relationship between SCKOUT, SCKIN and
BLANK.
ADV7160/ADV7162The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 19 shows a
suggested frame buffer to ADV7160/ADV7162 interface. This is a
minimum chip solution and allows the ADV7160/ADV7162 con-
trol the overall graphics system clocking and synchronization.
Figure 19. ADV7160/ADV7162 Interface Using SCKIN
and SCKOUT
PLLThe on-board PLL can be used as an alternative clock source.
This eliminates the need for an external high speed clock gen-
erator such as a crystal oscillator. With the PLL, it is possible to
generate an internal clock whose frequency is a multiple of the PLL
reference frequency (PLLREF). Internal PLL operation is selected
by setting CR56 of Command Register 5 to Logic “1.” The PLL
registers can be programmed to set up the frequency required.
The block diagram of the Phase Locked Loop is shown in Fig-
ure 20. The blocks consist of a phase frequency detector, a
charge pump, a loop filter, a voltage controlled oscillator and a
programmable divider.
PLLREF
FVCOFigure 20. PLL Block Diagram
The phase frequency detector drives the voltage controlled oscil-
lator (VCO), to a frequency that will cause the two inputs to the
phase frequency detector to be matched in frequency and phase.
The corresponding output of the VCO can be calculated as:
VCO = PLLREFFeedback Divider
Reference Divider
The Reference Divider is set by a combination of the contents of
the PLL R Register and the RSEL bit. The PLL R Register has
a resolution of 7 bits. It is programmed by setting the PLL R
Register located at Control Register address 00CH . The PLL
R Register can be set from 01H to 7FH. It should not be set to
00H. If this register contains 00H, then the PLL stops. There-
fore, the Reference Divider can be set from 3 to 129 in steps of
one, or from 130 to 258 in steps of two by setting the RSEL bit.
The RSEL bit is accessed by changing Bit PCR1 of the PLL
Control Register. The Feedback Divider is set by a combina-
tion of the contents of the PLL V Register, the VSEL bit and
the S value. The S value is set up in PCR7 and PCR6 of the
PLL Command Register. This S value allows a better resolu-
tion when setting the Feedback Divider value. The PLL V Reg-
PLL V Register can be set from 01H to 7FH. It should not be
set to 00H. If this register contains 00H, then the PLL stops.
Therefore the feedback divider can be set from 12 to 519 in
steps of one, or from 520 to 1038 in steps of two by setting the
VSEL bit. The VSEL bit is accessed by changing bit PCR2 of
the PLL Control Register. The P counter divides the output
from the oscillator by 1, 2, 4 or 8 as determined by PSEL1 and
PSEL0 which are set in bits PCR5 and PCR4 of the PLL Con-
trol Register. This post-scaler is useful in the generation of
lower frequencies as the VCO has been optimized for high
frequency operation.
PLLREF
VCO
VCO/2
VCO/4
VCO/8
PSEL1PSEL0
FOUTFigure 21.PLL Transfer Function
The transfer function of the PLL can be summarized by the
block diagram shown in Figure 21.
To optimize the performance of the on-board PLL, the follow-
ing criteria should be followed:
900 kHz< PLLREF< 40 MHz
300 kHz< FPD< 10 MHz
120 MHz< FVCO< 260 MHz
For FVCO > 220 MHz, VSEL should be programmed to logic “0.”
Any lower frequency output can be achieved by using the output
divider.
A jitter performance graph as a function of both FPD and FVCO is
illustrated in Figure 22. It can be seen that jitter decreases with
increasing FVCO and also that jitter decreases with increasing
FPD. For each FOUT, the user should firstly maximize FVCO us-
ing the output divider and then pick PLLREF and reference di-
vide to maximize FPD. When generating multiple output
frequencies from one PLLREF value, an iterative process should
be used to find the PLLREF value that gives the best trade off be-
tween jitter performance and FOUT accuracy.
COLOR VIDEO MODESThe ADV7160/ADV7162 supports a number of color video
modes all at the maximum video rate.
Command bits CR27–CR24 of Command Register 2 along with
bit MR11 of Mode Register 1 determine the color mode. Seven
color modes use the Color Palette, and three of them bypass the
palette and control the DACs directly.
24-Bit True Color
(CR27, CR26, CR25, CR24 = 1, 1, 1, 0)The part is set to 24-bit/30-bit “Gamma” True-Color operation
with MR11 set to Logic “1” and direct 24-bit True-Color op-
eration with MR11 set to Logic “0.” The pixel port accepts 24
bits of color data which is directly mapped to the Look-Up
Table RAM. With MR11 set to Logic “1,” the Look-Up Table
is configured as a 256 location by 30 bits deep RAM (10 bits
each for Red, Green and Blue), the RAM is preloaded with a
user determined, nonlinear function, such as a gamma correc-
tion curve and the output of the RAM drives the DACs with
30-bit data. With MR11 set to Logic “0,” the Look-Up Table is
configured as a 256 location by 24 bits deep RAM (8 bits each
for Red, Green and Blue), the RAM is preloaded with a linear
function and the output of the RAM drives the DACs with 24-
bit data.
24-BIT COLOR
24-BIT TO 30-BIT
LOOK-UP TABLE30-BIT COLOR
ANALOG VIDEO
OUTPUTS
RED
OUT
GREEN
OUT
BLUE
OUTFigure 23.24-Bit to 30-Bit True-Color Configuration
16-Bit True Color
(CR27, CR26, CR25, CR24 = 1, 0, 1, 1)The part is set to 16-bit True-Color operation. The pixel port
accepts 16 bits of color data which is mapped to the 5 LSBs of
each of the red and blue palettes of the Look-Up-Table RAM,
and 6 LSBs of the green palette of the Look-Up-Table RAM.
With MR11 set to Logic “1,” the Look-Up Table is configured
as a 64 location by 30 bits deep RAM (10 bits each for Red,
Green and Blue) and the output of the RAM drives the DACs
with 30-Bit data, allowing the display of 16-bit Gamma-
Corrected True-Color Images. With MR11 set to Logic “0,”
the Look-Up Table is configured as a 64 location by 24 bits
deep RAM (8 bits each for Red, Green and Blue); and the out-
put of the RAM drives the DACs with 24-bit data, allowing the
display of 16-bit True-Color Images.
15-Bit True Color
(CR27, CR26, CR25, CR24 = 1, 1, 0, 0 or 1, 1, 0, 1)The part is set to 15-bit True-Color operation. The pixel port
accepts 15 bits of color data which is mapped to the 5 LSBs of
each of the red, green and blue palettes of the Look-Up Table
RAM. With MR11 set to Logic “1,” the Look-Up Table is con-
figured as a 32 location by 30 bits deep RAM (10 bits each for
DACs with 30-bit data, allowing the display of 15-bit Gamma-
Corrected True-Color Images. With MR11 set to Logic “0,”
the Look-Up Table is configured as a 32 location by 24 bits
deep RAM (8 bits each for Red, Green and Blue) and the out-
put of the RAM drives the DACs with 24-bit data, allowing the
display of 15-bit True-Color Images.
15-BIT COLOR
DATA
15-BIT TO 24-BIT
LOOK-UP TABLEANALOG VIDEO
OUTPUTS
RED
OUT
GREEN
OUT
BLUE
OUT
24-BIT COLOR
DATAFigure 24. 15-Bit to 24-Bit True-Color Configuration
8-Bit Pseudo Color
(CR27, CR26, CR25, CR24 = 0, 0, 0, 0 or 0, 1, 0, 0 or 1, 0, 0, 0)This mode sets the part into 8-bit Pseudo-Color operation. The
pixel port accepts 8 bits of pixel data, from either the red, blue
or green channel. With MR11 set to Logic “1,” a 30-bit word is
indexed in the Look-Up Table RAM. The Look-Up Table is
configured as a 256 location by 30 bits deep RAM (10 bits each
for Red, Green and Blue). The output of the RAM drives the
DACs with 30-bit data. With MR11 set to Logic “0,” a 24-Bit
word is indexed in the Look-Up Table RAM. The Look-Up
Table is configured as a 256 location by 24 bits deep RAM (8
bits each for Red, Green and Blue). The output of the RAM
drives the DACs with 24-bit data. This mode allows for the dis-
play of 256 simultaneous colors out of a total palette of millions
of addressable colors.
Figure 25. 8-Bit to 30-Bit Pseudo-Color Configuration
PIXEL PORT MAPPINGThe pixel data to the ADV7160/ADV7162 is automatically
mapped in the parts pixel port as determined by the pixel data
mode programmed (Bits CR27–CR24 of Command Register 2).
Pixel data in the 24-bit True-Color modes is directly mapped to
the 24 color inputs R7–R0, G7–G0 and B7–B0.
There is one mode of operation for 16-bit True Color. Data is
input to the device over the red and green color ports (R7–R0
and G7–G0) and is internally mapped to LUT Locations 0–63
according to Figure 26. (Note: Data on unused pixel inputs is
ADV7160/ADV7162
BLUE
DAC
GREEN
DAC
RED
DAC
PIXEL
INPUT
DATA
PIN
ASSIGN-
MENTS
DATA
LATCHED
PIXEL
PORT
DATA
INTERNALLY
SHIFTED
TO 5 OR 6 LSBs
DATA LATCHES
FIRST 32 OR 64
LOCATIONS
OF RAM Figure 26. 16-Bit True-Color Mapping using R7–R0
and G7–G0
BLUE
DAC
GREEN
DAC
RED
DAC
PIXEL
INPUT
DATA
PIN
ASSIGN-
MENTS
DATA
LATCHED
PIXEL
PORT
DATA
INTERNALLY
SHIFTED
TO 5 LSBs
DATA LATCHES
FIRST 32
LOCATIONS
OF RAM Figure 27. 15-Bit True Color Mapping using R7–R3, G7–G3
BLUE
DAC
GREEN
DAC
RED
DAC
PIXEL
INPUT
DATA
PIN
ASSIGN-
MENTS
DATA
LATCHED
PIXEL
PORT
DATA
INTERNALLY
SHIFTED
TO 5 LSBs
DATA LATCHES
FIRST 32
LOCATIONS
OF RAM Figure 28. 15-Bit True-Color Mapping using R6–R0
and G7–G0
The part has two modes of operation for 15-bit True Color. In
the first mode, data is input to the device over the red, green
and blue channel (R7–R3, G7–G3 and B7–B3) and is internally
mapped to Locations 0 to 31 of the Look-Up Table (LUT)
according to Figure 27.
In the second mode, data is input to the device over just two of
the color ports, red and green (R7–R0 and G7–G0) and is inter-
nally mapped to LUT Locations 0 to 31 according to Figure 30.
(Note: Data on unused pixel inputs is ignored.)
There are three modes of operation for 8-bit Pseudo Color.
Each mode maps the input pixel data differently. Data can be
input into one of the three color channels, R7–R0 or G7–G0 or
B7–B0.
In 24-bit Palette Bypass Mode, the red, blue and green color
channels bypass the Pixel Mask and the Color Palette. Each 8-
bit color channel is mapped onto the 8 MSBs of the correspond-
ing 10-bit DAC input. The two LSBs on each DAC are zeros.
The Bypass Mode can be selected in two ways, by using CR27–
CR24 of Command Register 2 or on a pixel by pixel basis using
the PS inputs (ADV7160 only).
In 16-bit Palette Bypass Mode, the color channels bypass the
Pixel Mask and the Color Palette. The 8-bits of red pixel data
and 8-bits of green pixel data are mapped onto the 5 MSBs of
the red and blue DAC input and the 6 MSBs of the green DAC
input as shown in Figure 29. The remaining LSBs on each
DAC are zeros. The Bypass Mode can be selected in two ways,
by using CR27–CR24 of Command Register 2 or on a pixel by
pixel basis using the PS inputs (ADV7160 only).
PIXEL
INPUT
DATA
PIN
ASSIGN-
MENTS
DATA
LATCHED
PIXEL PORT
DATA LATCHED
TO DAC INPUTS
IOR
IOG
IOB Figure 29. 16-Bit True-Color in Bypass Mode using R7–R0
and G7–G0
PIXEL
INPUT
DATA
PIN
ASSIGN-
MENTS
DATA
LATCHED
PIXEL PORT
DATA LATCHED
TO DAC INPUTS
IOR
IOG
IOBIn 15-bit Palette Bypass Mode, the color channels bypass the
Pixel Mask and the Color Palette. The 7 bits of red pixel data
and 8 bits of green pixel data are mapped onto the 5 MSBs of
the red, green and blue DAC input as shown in Figure 30. The
remaining LSBs on each DAC are zeros. The Bypass Mode can
be selected in two ways, by using CR27–CR24 of Command
Register 2 or on a pixel by pixel basis using the PS inputs
(ADV7160 only).
MultiplexingThe on-board multiplexers of the ADV7160/ADV7162 elimi-
nate the need for external data serializer circuits. Multiple video
memory devices can be connected, in parallel, directly to the de-
vice. Figure 31 shows four memory banks of 50 MHz memory
connected to the ADV7160, running in 4:1 multiplex mode,
giving a resultant pixel or dot clock rate of 200 MHz. Instead of
having to provide a new pixel at the input every 5 ns, four pixels
are provided together every 20 ns. The input multiplexer takes
the four pixels latched in parallel, and selects them one at a time
to produce a pixel stream at the pixel clock rate. In 4:1 mode,
the pixels are selected in the sequence A, B, C, D, cycling continu-
ously. In 2:1 mode, the A and B pixels are selected. The 8:1
mode is only available in 8-bit Pseudo-Color Mode. BLANK,
SYNC, ODD/EVEN and TRISYNC are not multiplexed and
can only change on a 1, 2, 4 or 8 pixel boundary depending on
the multiplex mode.
On the rising edge of LOADIN, all the pixel port inputs are
latched into the ADV7160/ADV7162. The LOADIN frequency
must be a divided down frequency of the pixel clock frequency.
This can be achieved using LOADOUT to directly drive
LOADIN as LOADOUT provides the correct frequency re-
quired, or drive LOADIN after delay through some external cir-
cuitry.
200MHz
(4 × 50MHz)
VIDEO MEMORY/
FRAME BUFFER
ADV7160/ADV7162
VRAM (BANK A)
VRAM (BANK B)
VRAM (BANK C)
VRAM (BANK D) Figure 31.Direct Interfacing of Video Memory to
ADV7160/ADV7162
8-Bit Pseudo Color in 8:1 Multiplexing ModeWhen 8:1 Multiplexing Mode is selected by setting Bit CR37 of
Command Register 3 to Logic “1” and bit CR36 of Command
Register 3 to Logic “0,” the ADV7160/ADV7162 goes into 8-
Bit Pseudo-Color Mode irrespective of the Color Mode selected
by Bits CR27 to CR24 in Command Register 2. Hence
LOADOUT operates at fCLOCK/8. Eight 8-bit pixels are latched
in parallel by the rising edge of LOADIN. These 8-bit pixels
are then selected, one at a time, to produce an 8-bit pixel stream
which passes through the Pixel Mask to address the LUT. The
ADV7160/ADV7162
MICROPROCESSOR (MPU PORT)The ADV7160/ADV7162 supports a standard MPU Interface.
All the functions of the part are controlled via this MPU port.
Direct access is gained to the Address Register, Mode Register
and all the Control Registers as well as the Color Palette. The
following sections describe the setup for reading and writing to
all of the devices registers.
MPU InterfaceThe MPU interface (Figure 33) consists of a bidirectional, 10-
bit wide databus and interface control signals CE, C0, C1 and
R/W. The 10-bit wide databus is user configurable as illustrated.
Table I.Data-Bus Width
Register MappingThe ADV7160/ADV7162 contains a number of on-board regis-
ters including the Mode Register (MR17–MR10), Address Reg-
ister (A10–A0) and many Control Registers as well as Color
Palette Registers. These registers control the entire operation of
the part. Figure 34 shows the internal register configuration.
Control lines C1 and C0 determine which register the MPU is
accessing. C1 and C0 also determine whether the Address Reg-
ister is pointing to the color registers and Look-Up Table RAM
or the control registers. If C1, C0 = 1, 0 the MPU has access to
whatever control register is pointed to by the Address Register
(A10–A0). If C1, C0 = 0, 1 the MPU has access to the Look-
Up Table RAM (Color Palette) or the Overlay Palette through
the associated color registers. The CE input latches data to or
from the part.
The R/W control input determines between read or write ac-
cesses. The truth tables show all modes of access to the various
registers and color palette for both the 8-bit wide databus con-
figuration and 10-bit wide data bus configuration. It should be
noted that after power-up, the devices MPU port is automati-
cally set to 10-bit wide operation (see Power-On Reset section).
Figure 32.8-Bit Pseudo Color in 8:1 Multiplexing Mode
The unused Blue pixel inputs are used, in this mode, to provide
8 extra PS inputs. These PS inputs provide 2 bits after 8:1 mul-
tiplexing. The PS inputs can be used as Overlay or Palette Se-
lect inputs.
G7–G0
R7–R0
G7–G0
R7–R0
G7–G0
R7–R0
G7–G0
R7–R0
PS1–PS0
B1–B0
PS1–PS0
B1–B0
PS1–PS0
B1–B0
PS1–PS0
B1–B030-BIT COLOR
ANALOG VIDEO
OUTPUTS
RED
OUT
GREEN
OUT
BLUE
OUTCER/W
10 (8+2)
DATA TO
PALETTESD9–D0
ADDRESS
REGISTER
MODE
REGISTER
CONTROL REGISTERS
COLOR REGISTERS
