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ADUM1310ADIN/a17avaiTriple-Channel Digital Isolators


ADUM1310 ,Triple-Channel Digital IsolatorsSPECIFICATIONS ADuM1310, Total Supply Current, 1Three Channels DC to 2 Mbps VDD1 ..
ADUM1310BRWZ-RL , Triple-Channel Digital Isolator with Programmable Default Output
ADUM1310BRWZ-RL , Triple-Channel Digital Isolator with Programmable Default Output
ADUM1400ARW ,Quad-Channel Digital IsolatorsFEATURES Low power operation The ADuM140x are 4-channel digital isolators based on Analog 5 V opera ..
ADUM1400ARWZ ,Quad-Channel Digital IsolatorsFEATURES Low power operation The ADuM140x are 4-channel digital isolators based on Analog 5 V opera ..
ADUM1400ARWZ-RL ,Quad-Channel Digital Isolator (4/0 Channel Directionality)Characteristics .... 13 Ordering Guide .. 21 Recommended Operating Conditions 13 Absolute Maximum ..
AM27C020-55DC , 2 Megabit (256 K x 8-Bit) CMOS EPROM
AM27C040 , 4 Megabit (512 K x 8-Bit) CMOS EPROM
AM27C040-120DE , 4 Megabit (512 K x 8-Bit) CMOS EPROM
AM27C040-120DI , 4 Megabit (512 K x 8-Bit) CMOS EPROM
AM27C040-120PC , 4 Megabit (512 K x 8-Bit) CMOS EPROM
AM27C040-150DE , 4 Megabit (512 K x 8-Bit) CMOS EPROM


ADUM1310
Triple-Channel Digital Isolators
ANALOG
DEVICES
Triple-Channel Digital Isolators
AlhIhll13Whlha1311
FEATU RES
Low power operation
5 V operation
1.7 mA per channel maximum @ o Mbps to 2 Mbps
4.0 mA per channel maximum @ 2 Mbps to 10 Mbps
3 V operation
1.0 mA per channel maximum @ o Mbps to 2 Mbps
2.1 mA per channel maximum o 2 Mbps to 10 Mbps
Bidirectional communication
3 V/5 V level translation
Schmitt trigger inputs
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/ps
16-lead, RoHS-compliant, SOIC wide body package
8.1 mm external creepage
Safety and regulatory approvals
UL recognition: 2500 V rms for T minute per UL 1577
CSA Component Acceptance Notice #SA
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
View = 560 V peak working voltage
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM131xl are 3-channel digital isolators based on
Analog Devices, Inc., iCoupler" technology. Combining high
speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, maximum operating temperature, and
lifetime effects are eliminated with the simple iCoupler digital
interfaces and stable performance characteristics. The need for
external drivers and other discrete components is eliminated
with these iCoupler products. Furthermore, Coupler devices
consume one-tenth to one-sixth the power of optocouplers at
comparable signal data rates. The iCoupler also offers higher
channel densities and more options for channel directionality.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
tesponsibileyisassumed byAnalog Devicesfor its use. nor%ranyinhingementsofpatentsurother
rights of third partiesthat may Iesultfrom itsusa Spedfiotions subject to thangewithout notice No
license is granted by implication or otherwise under any patent or patent rights of Analog Davies.
Trademarks and registered trademarks arethe pmpertyof their respective owners.
FUNCTIONAL BLOCK DIAGRAMS
VDD1 o ADUM1310
Figure 2. ADuM 131 l
The ADuMl31x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
up to 10 Mbps (see the Ordering Guide). All models operate
with the supply voltage on either side ranging from 2.7 V to
5.5 V, providing compatibility with lower voltage systems as well
as enabling voltage translation functionality across the isolation
barrier. All products allow the user to predetermine the default
output state in the absence of input me power with a simple
control pin. Unlike other optocoupler alternatives, the ADuM131x
isolators have a patented refresh feature that ensures dc correctness
in the absence of input logic transitions and during power-up/
power-down conditions.
l . Patents 5,952,849; 6,873,065; and 7,075,329. Other patents
pending.
One Technology Way, P.0. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781 .329.4700
Fax: 781.461.3113 ©2005-20T2 Analog Devices, Inc. All rights reserved.
h0ulil131illh0uhd1311
TABLE OF CONTENTS
Features m............................................................................................. 1
Applications _...................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description P........................................................................ 1
Revision History F.............................................................................. 2
Specifications w.................................................................................... 3
Electrical Characteristics-S V Operation ................................ 3
Electrical Characteristics- V Operation ................................ 5
Electrical Characteristics-Mixed 5 V/ 3 V or 3 V/5 V
Operation _...................................................................................... 7
Package Characteristics K............................................................ 10
Regulatory Information _............................................................ 10
Insulation and Safety-Related Specifications .......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics _......................................................... 11
REVISION HISTORY
3/12-Rev. G to Rev. H
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section T................................................................ 1
Change to PC Board Layout Section ............................................ 18
Updated Outline Dimensions ....................................................... 21
6/07-Rev. F to Rev. G
Updated VDE Certification Throughout ...................................... 1
Changes to Features and Applications ........................................... 1
Changes to DC Specifications in Table 1 ....................................... 3
Changes to DC Specifications in Table 2.... ... 5
Changes to DC Specifications in Table 3 ....................................... 7
Changes to Regulatory Information Section .............................. 10
Added Table 10 _.............................................................................. 12
Added Insulation Lifetime Section .............................................. 19
1/07-Rev. E to Rev. F
Added ADuM1311 B............................................................ Universal
Changes to Typical Performance Characteristics Section ......... 16
Changes to Ordering Guide .......................................................... 20
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings _........................................................ 12
ESD Caution ................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 16
Applications Information w............................................................. 18
PC Board Layout Q....................................................................... 18
Propagation Delay-Related Parameters ................................... 18
DC Correctness and Magnetic Field Immunity ..................... 18
Power Consumption B................................................................. 19
Insulation Lifetime _.................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide w......................................................................... 21
10/06-Rev. D to Rev. E
Removed ADuM1410 Q....................................................... Universal
Updated Format F................................................................. Universal
Change to Figure 3 ......................................................................... 10
Changes to Table 10 ....................................................................... 10
Changes to Application Information Section ............................. 12
Updated Outline Dimensions B...................................................... 18
Changes to Ordering Guide w......................................................... 18
3/06-Rev. C to Rev. D
Added Note 1; Changes to Figure 2 ..........
Changes to Absolute Maximum Ratings ..................................... 11
l 1/05-Revision C: Initial Version
Rev. H l Page 2 of 24
A0uN1310/Mulil131 1
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS-S V OPERATION
4.5 V S Vom S 5.5 V, 4.5 V S VDDz S 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, Vom = Vnm = 5 V. All voltages are relative to their respective grounds.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
ADuM1310,Total Supply Current,
Three Channels"
DC to 2 Mbps
Vom Supply Current |DD1(Q) 2.4 3.2 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current 1002 (Q) 1.2 1.6 mA DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Grade Only)
Vom Supply Current |DD1<10) 6.6 9.0 mA 5 MHz logic signal frequency
VDD2 Supply Current lax (10) 2.1 3.0 mA 5 MHz logic signal frequency
ADuM1311,Total Supply Current,
Three Channels"
DC to 2 Mbps
Vom Supply Current |DD1(Q) 2.2 2.8 mA DC to 1 MHz logic signal
frequency
Van Supply Current 1002 (Q) 1.8 2.4 mA DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Grade Only)
Voor Supply Current lromom 4.5 5.7 mA 5 MHz logic signal frequency
VDD2 Supply Current lax (10) 3.5 4.3 mA 5 MHz logic signal frequency
For All Models
Input Currents IIA, la, K, |CTRL1, -1 0 +0.01 +10 LIA 0 V S VIA, Va, VIC S Vom or Wrv,
ICTRLz, IDISABLE 0V S Vcnv,Vcnv S Vom or VDDZ,
0 V S VDISABLE S Vom
Logic High Input Threshold w, 2.0 V
Logic Low Input Threshold VIL 0.8 V
Logic High Output Voltages VOAH, VOBH, VOCH (Vom or V002) - 0.1 5.0 V lo, = -20 “A, W = VIxH
Mom or VDD2) - 0.4 4.8 V lo, = -4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V lo, = 20 yA, Vs = VIxL
0.2 0.4 V on = 4 mA, Nh, = VIXL
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay' tpHL, tPLH 20 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, ItPLH - tpml“ PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tpsx 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching' tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels
ADuM131xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay' tpHL, tPLH 20 30 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tpLH - tPHL|4 PWD 5 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tpsx 30 ns CL = 15 pF, CMOS signal levels
Rev. H l Page 3 of 24
h0ulil131illh0uhd1311
Parameter Symbol Min Typ Max Unit Test Conditions
ChanneI-to-Channel Matching, tpsxco 5 ns CL: 15 pF, CMOS signal levels
Codirectional Channels'
Channel-to-Channel Matching, tPSKOD 6 ns CL: 15 pF, CMOS signal levels
Opposing-Directional Channels6
For All Models
Output Rise/FallTIme (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-ModeTransient Immunity ICMH| 25 35 kV/ps W = Vom orVDnz,ch = 1000 V,
at Logic High Output transient magnitude = 800 V
Common-Mode/it Immunity ICMLI 25 35 kV/ps le = 0V, VCM = 1000 V,
at Logic Low Output7 transient magnitude = 800V
Refresh Rate f, 1.2 Mbps
Input Enable Times tENABLE 2.0 [IS VIA, Va, VIC = 0 V or Vom
Input Disable Times tDlSABLE 5.0 L15 VIA, Va, VIC = 0 V or '
Input Supply Current per Channel, IDDI (Q) 0.50 0.73 mA
Quiescent'
Output Supply Current per Channel, looom) 0.38 0.53 mA
Quiescent'
Input Dynamic Supply Current IDDI (D) 0.12 mA/
perChannel1O Mbps
Output Dynamic Supply Current per IDDo(D) 0.04 mA/
Channel" Mbps
l The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total Vnm and Vunz supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
, The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge ofthe le signal to the 50% level of the falling edge of the Vo, signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the W signal to the 50% level of the rising edge of the Vox signal.
5 tPsx is the magnitude ofthe worst-case difference in tve or tptH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining Vo > 0.8 Voor CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining Vo < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence ofany input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output ofthat channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL, logic state (see Table 13).
9 bo, (m is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
m Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H l Page 4 of 24
A0uN1310/Mulil1311
ELECTRICAL CHARACTERISTICS-S V OPERATION
2.7 V S me S 3.6 V, 2.7 V S me S 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, me = Vnm = 3.0 V. All voltages are relative to their respective ground.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
ADuM1310,Total Supply Current,
Three Channels"
DC to 2 Mbps
Voor Supply Current |DD1(Q) 1.2 1.6 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current looz (Q) 0.8 1.0 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ Grade Only)
Vom Supply Current lam (10) 3.4 4.9 mA 5 MHz logic signal frequency
VDD2 Supply Current |DD2(10) 1.1 1.3 mA 5 MHz logic signal frequency
ADuM1311,Total Supply Current,
Three Channels1
DC to 2 Mbps
Vom Supply Current low (Q) 1.0 1.6 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current lam (Q) 0.9 1.4 DC to 1 MHz logic signal frequency
10 Mbps (BRWZ Grade Only)
Vom Supply Current lam (10) 2.5 3.5 mA 5 MHz logic signal frequency
Vom Supply Current |Doz(10) 1.9 2.6 5 MHz logic signal frequency
For All Models
Input Currents IIA, Ina, Ilc, Icmn, -1 0 +0.01 +10 LIA O V S VIA, V13, Mc S V001 or V002,
ICTRLZ, IDISABLE 0 V S VCTRL1, VCTRLZ S Vom or V002,
O V S VDISABLE S Vom
Logic High Input Threshold w, 1.6 V
Logic Low Input Threshold VIL 0.4 V
Logic High Output Voltages VOAH, Vow, VOCH (Wo, or V002) - 0.1 3.0 V lo, = -20 PA, le = leH
(VDD1 or V002) - 0.4 2.8 V ko, = -4 mA, W = leH
Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V lo, = 20 PA, le = VIxL
0.2 0.4 V kox = 4 mA, W = VIxL
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width2 PW 1000 ns Cr, = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay' tPHL, tPLH 20 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, ItPLH - tPHLI“ PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching" tpsxco/oo 50 ns CL = 15 pF, CMOS signal levels
ADuM131xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay" hm, hm 20 30 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, ItPLH - tPHL|4 PWD 5 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tpsx 30 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, tpsxco 5 ns CL = 15 pF, CMOS signal levels
Codirectional Channels'
Channel-to-Channel Matching, tpsxoo 6 ns CL = 15 pF, CMOS signal levels
Opposing-Directional Channels'
Rev. H l Page 5 of 24
h0ulil131illh0uhd1311
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Rise/Fall Time (10% to 90%) te/ts 2.5 ns CL = 15 pF, CMOS signal levels
Common-ModeTransient Immunity ICMHI 25 35 kV/ps le =VDm orVDoz,VcM =1000V,
at Logic High Output transient magnitude = 800 V
Common-Mode Transient Immunity ICMLI 25 35 kV/ps le = 0 V, VCM = 1000 V,
at Logic Low Output7 transient magnitude = 800 V
Refresh Rate f, 1.1 Mbps
Input Enable Time3 tENABLE 2.0 ps VIA, VIB, VIC = 0 V or V001
Input Disable Times tDISABLE 5.0 [IS VIA, Va, VIC = 0 V or V001
Input Supply Current per Channel, loom) 0.25 0.38 mA
Quiescent'
Output Supply Current per Channel, Inomo) 0.19 0.33 mA
Quiescent9
Input Dynamic Supply Current |DD|(D) 0.07 mA/
perChannel1O Mbps
Output Dynamic Supply Current |DDO(D) 0.02 mA/
perChannel1O Mbps
l The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total Vum and V002 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
, The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge ofthe Vix signal to the 50% level of the falling edge of the Vox signal. tram propagation delay is
measured from the 50% level ofthe rising edge ofthe le signal to the 50% level of the rising edge of the Vox signal.
5 tess is the magnitude ofthe worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining Vo > 0.8 Voor CM is the maximum common-mode voltage slew rate
that can be sustained while maintaining Vo < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence ofany input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output ofthat channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRLz logic state (see Table 13).
9 lame; is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H l Page 6 of 24
A0uN1310/Mulil1311
ELECTRICAL CHARACTERISTICS-MIXED 5 VB V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V S Vnm S 5.5 V, 2.7 V S Vom S 3.6 V; 3 V/5 V operation: 2.7 V S VDm S 3.6 V, 4.5 V S Vnm S 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; me = 3.0 V, me = 5 V or me = 5 V, me = 3.0 V. All voltages are relative to their respective ground.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
ADuM1310,Total Supply Current,
Three Channels‘
DC to 2 Mbps
Vom Supply Current 1001(0)
5 W3 V Operation 2.4 3.2 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 1.2 1.6 mA DC to 1 MHz logic signal
frequency
Vax Supply Current 1002(0)
5 W3 V Operation 0.8 1.0 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 1.2 1.6 mA DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Grade Only)
Wm Supply Current bm (10)
5 W3 V Operation 6.5 8.2 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal frequency
V002 Supply Current boa (10)
5 W3 V Operation 1.1 1.3 mA 5 MHz logic signal frequency
3 V/5 V Operation 1.9 2.2 mA 5 MHz logic signal frequency
ADuM1311,Total Supply Current,
Three Channels)
DC to 2 Mbps
Wm Supply Current low (Q)
5 W3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal
frequency
Voos, Supply Current low (Q)
5 W3 V Operation 0.9 1.4 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 1.8 2.4 mA DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Grade Only)
Vom Supply Current low (10)
5 W3 V Operation 4.5 5.7 mA 5 MHz logic signal frequency
3 V/5 V Operation 2.5 3.5 mA 5 MHz logic signal frequency
VDD2 Supply Current boa (10)
5 W3 V Operation 1.9 2.6 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.5 4.3 mA 5 MHz logic signal frequency
For All Models
Input Currents u, IIB, Ilc, law, -1 0 +0.01 +10 pA O V S VIA, V's, VIC S Vom or VDDZ,
|CTRL2, IDISABLE 0 V S VCTRL], VCTRLZ S Vom or V002,
0 V S VDISABLE S Vom
Logic High InputThreshold w,
Voar = 5 V Operation 2.0 V
Voar = 3 V Operation 1.6 V
Rev. H l Page 7 of 24
h0ulil131illh0uhd1311
Parameter Symbol Min Typ Max Unit Test Conditions
Logic Low Input Threshold VIL
Voox = 5 V Operation 0.8 V
Voox = 3 V Operation 0.4 V
Logic High Output Voltages VOAH,VOBH, VOCH (V001 or V002) - 0.1 Nom orVax) V lo, = -20 PIA, W = leH
(V001 or V002) - 0.4 (V001 orVax) - 0.2 V lo, = -4 mA, le = VIxH
Logic Low Output Voltages Von, Val, Voa 0.0 0.1 V lo, = 20 HA, le = VIxL
0.2 0.4 V lo, = 4 mA, le = leL
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL: 15 pF, CMOS signal levels
Propagation Delay4 tpHL, tPLH 25 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion loo, - tpHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tpsx 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels
ADuM131xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL: 15 pF, CMOS signal levels
Propagation Delay' tpHL, tpLH 20 60 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |th - tpHL|4 PWD 5 ns CL = 15 pF, CMOS signal levels
Change vs.Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tess 30 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, tpsxco 5 ns CL = 15 pF, CMOS signal levels
Codirectional Channels6
ChanneI-to-Channel Matching, tpsxoo 6 ns CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
For All Models
Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels
5 W3 V Operation 2.5 ns
3 V/5 V Operation 2.5 ns
Common-ModeTransient ICMHI 25 35 kV/ps W = Vom or Vom, VCM = 1000 V,
Immunity at Logic High Output7 transient magnitude = 800V
Common-ModeTransient ICMLI 25 35 kV/ps W = 0V, VCM = 1000 V,
Immunity at Logic Low Output7 transient magnitude = 800V
Refresh Rate f,
5 W3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Enable Time8 tENABLE 2.0 us VIA, Vns, Vuc, Vo = O V or Voor
Input Disable Times tDISABLE 5.0 ys VIA, Va, VIC, Vo = 0 V or Voor
Input Supply Current per Channel,
Quiescent'
Voox = 5 V Operation IDDI (Q) 0.50 0.73 mA
VDDX = 3 V Operation IDDI (Q) 0.25 0.38 mA
Output Supply Current per
Channel, Quiescent9
Voox = 5 V Operation IDDo (Q) 0.38 0.53 mA
Voox = 3 V Operation looo (Q) 0.19 0.33 mA
Input Dynamic Supply Current per low (D)
Channel"'
Voox = 5 V Operation 0.12 mA/
Voox = 3 V Operation 0.07 mA/
Rev. H l Page 8 of 24
A0uN1310/Mulil131 l
Parameter Symbol Min Typ Max Unit TestConditions
Output Dynamic Supply Current IDDI (D)
per Channel"
Voox = 5 V Operation 0.04 mA/
Vonx = 3 V Operation 0.02 mA/
l The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total Vom and VDDz supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the Nh, signal to the 50% level of the falling edge of the Vex signal. tsv, propagation delay is
measured from the 50% level of the rising edge of the le signal to the 50% level of the rising edge of the V0): signal.
5 tess is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value ofthe difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining ( > 0.8 me. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining Vo < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
3 Input enable time is the duration from when VDiSABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL: logic state (see Table 13).
9 Iowa; is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H l Page 9 of 24
h0ulil131illh0uhd1311
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)1 Rio 1012 fl
Capacitance (Input-to-Output)‘ Cro 2.2 pF f= 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Case Thermal Resistance
Side1 (ha 33 ''C/W Thermocouple located at center of package underside
Side 2 eJCO 28 ''C/W
l The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuMl31x have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for
recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL CSA VDE
Recognized Under 1577 Component Approved under CSA Component Certified according to DIN V VDE V 0884-1 0
Recognition Program" Acceptance Notice #SA (VDE V 0884-10): 2006-122
Double/Reinforced Insulation, 2500 V rms Basic insulation per CSA 60950-1-03 and Reinforced insulation, 560 V peak
Isolation Voltage IEC 60950-1, 800 V rms(1131 V peak)
maximum working voltage
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
l In accordance with UL1577,each ADuM131x is proof-tested by applying an insulation test voltage 23000 V rms for 1 sec (current leakage detection limit = 5 pA).
2 In accordance with DIN VVDE V 0884-10, each ADuM131x is proof-tested by applying an insulation test voltage 21050 V peak for 1 second (partial discharge detection
limit = 5 pC). The asterisk C) marked on the component designates DIN V VDE V 0884-1 0 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms I-minute duration
Minimum External Air Gap (Clearance) L(IO1) 7.7 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(102) 8.1 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 1 12NDE 0303 Part 1
Isolation Group Illa Material Group (DIN VDE 0110, 1/89,Table 1)
Rev. H l Page 10 of 24
A0uN1310/Mulil1311
DIN V VDE V 0884-1 o (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
The ADuM131x isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is
ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 7.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage 3 150V rms I to IV
For Rated Mains Voltage 5 300 V rms I to Ill
For Rated Mains Voltage 5 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110,Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method B1 VIORM x 1.875 = Vim, 100% production test, tn. = 1 sec, VPR 1050 V peak
partial discharge < 5 pC
Input-to-Output Test Voltage, Method A VIORM X 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Vpn
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test Subgroup 2 VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tm = 10 sec VTR 4000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure;
see Figure 3
Case Temperature Ts 150 T
Side 1 Current ls, 265 mA
Side 2 Current lsz 335 mA
Insulation Resistance at Ts Vo = 500 V Rs >109 fl
350 RECOMMENDED OPERATING CONDITIONS
300 Table 8.
Parameter Symbol Min Max Unit
250 Operating Temperature TA -40 +105 "C
200 SupplyVoltages1 Wm, V002 2.7 5.5 V
Input Signal Rise and Fall Times 1.0 ms
SAF ETY-LIMITING CURRENT (mA)
0 50 100
CASE TEMPERATURE (°C)
magnetic fields.
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. H l Page 11 of 24
t All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
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